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參數(shù)資料
| 型號： | XCF08PV |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng) |
| 文件頁數(shù)： | 40/46頁 |
| 文件大?。?/td> | 525K |
| 代理商： | XCF08PV |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
40
R
CEO
06
Data Out
Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
10
D2
05
Output Enable
EN_EXT_SEL
31
Data In
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
EN_EXT_SEL has an internal 50K
Ω
resistive pull-up to V
CCO
to provide a logic 1 to the device if the pin is not driven.
25
H4
REV_SEL0
30
Data In
Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Revision Select control bits. The Revision Select[1:0] inputs
have an internal 50 K
Ω
resistive pull-up to V
to provide a
logic 1 to the device if the pins are not driven.
26
G3
REV_SEL1
29
Data In
27
G4
BUSY
12
Data In
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50 K
Ω
resistive pull-down to GND to provide a logic 0 to the device
if the pin is not driven.
5
C1
CLKOUT
08
Data Out
Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal, which is sourced from
either the internal oscillator or the CLK input pin. Each rising
edge of the selected clock source increments the internal
address counter if data is available, CE is Low, and
OE/RESET is High. Output data is available on the rising
edge of CLKOUT. CLKOUT is disabled if CE is High or
OE/RESET is Low. If decompression is enabled, CLKOUT is
parked High when decompressed data is not ready. When
CLKOUT is disabled, the CLKOUT pin is put into a high-Z
state. If CLKOUT is used, then it must be pulled High
externally using a 4.7 K
Ω
pull-up to V
CCO
.
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50 K
Ω
resistive
pull-up to V
CCJ
to provide a logic 1 to the device if the pin is
not driven.
9
C2
07
Output Enable
TMS
Mode Select
21
E2
TCK
Clock
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
20
H3
TDI
Data In
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50 K
Ω
resistive pull-up to V
CCJ
to provide a logic 1 to the device if
the pin is not driven.
19
G1
TDO
Data Out
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50K
Ω
resistive pull-up to V
to provide a logic 1 to the
system if the pin is not driven.
22
E6
VCCINT
+1.8V Supply. Positive 1.8V supply voltage for internal logic.
4, 15, 34
B1, E1,
G6
Table 14:
XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48)
(Continued)
Pin Name
Boundary
Scan Order
Boundary
Scan
Function
Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCF08PVG | Platform Flash In-System Programmable Configuration PROMS |
| XCF08PVO48 | Platform Flash In-System Programmable Configuration PROMS |
| XCF08PVO48C | Platform Flash In-System Programmable Configuration PROMS |
| XCF08PVOG48 | Platform Flash In-System Programmable Configuration PROMS |
| XCF08PVOG48C | Platform Flash In-System Programmable Configuration PROMS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCF08PVG | 制造商:XILINX 制造商全稱:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS |
| XCF08PVO48 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS |
| XCF08PVO48C | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XCF08PVO48C | 制造商:Xilinx 功能描述: |
| XCF08PVO48C0973 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
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