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參數(shù)資料
型號(hào)： XCF08PFSG48C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 9/35頁(yè)
文件大?。?/td> 0K
描述： IC PROM SRL 1.8V 8M GATE 48CSBGA
產(chǎn)品變化通告： Package Assemble Change 01/Jan/2007
標(biāo)準(zhǔn)包裝： 108
可編程類型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 8Mb
電源電壓： 1.65 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-BFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 48-CSP（8x9）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 601 (CN2011-ZH PDF)
其它名稱： 122-1453
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
17
R
TCYC
Clock period(6) (serial mode) when VCCO = 3.3V or 2.5V
30
–
25
–
ns
Clock period(6) (serial mode) when VCCO = 1.8V
67
–
25
–
ns
Clock period(6) (parallel mode) when VCCO = 3.3V or 2.5V
–
30
–
ns
Clock period(6) (parallel mode) when VCCO = 1.8V
–
30
–
ns
TLC
CLK Low time(3) when VCCO = 3.3V or 2.5V
10
–
12
–
ns
CLK Low time(3) when VCCO = 1.8V
15
–
12
–
ns
THC
CLK High time(3) when VCCO = 3.3V or 2.5V
10
–
12
–
ns
CLK High time(3) when VCCO = 1.8V
15
–
12
–
ns
TSCE
CE setup time to CLK (guarantees proper counting)(3)
when VCCO = 3.3V or 2.5V
20
–30–
ns
CE setup time to CLK (guarantees proper counting)(3)
when VCCO = 1.8V
30
–
ns
THCE
CE hold time (guarantees counters are reset)(5)
when VCCO = 3.3V or 2.5V
250
–
2000
–
ns
CE hold time (guarantees counters are reset)(5)
when VCCO = 1.8V
250
–
2000
–
ns
THOE
OE/RESET hold time (guarantees counters are reset)(6)
when VCCO = 3.3V or 2.5V
250
–
2000
–
ns
OE/RESET hold time (guarantees counters are reset)(6)
when VCCO = 1.8V
250
–
2000
–
ns
TSB
BUSY setup time to CLK when VCCO = 3.3V or 2.5V(8)
––
12
–
ns
BUSY setup time to CLK when VCCO = 1.8V(8)
––
12
–
ns
THB
BUSY hold time to CLK when VCCO = 3.3V or 2.5V(8)
––8–
ns
BUSY hold time to CLK when VCCO = 1.8V(8)
––8–
ns
TSXT
EN_EXT_SEL setup time to CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
300
–
ns
EN_EXT_SEL setup time to CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
300
–
ns
THXT
EN_EXT_SEL hold time from CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
300
–
ns
EN_EXT_SEL hold time from CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
300
–
ns
TSRV
REV_SEL setup time to CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
300
–
ns
REV_SEL setup time to CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
300
–
ns
THRV
REV_SEL hold time from CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
300
–
ns
REV_SEL hold time from CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
300
–
ns
Notes:
1.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
2.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels.
3.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
4.
If THCE High < 2 s, TCE = 2 s.
5.
If THOE Low < 2 s, TOE = 2 s.
6.
This is the minimum possible TCYC. Actual TCYC = TCAC + FPGA Data setup time. Example: With the XCF32P in serial mode with VCCO at
3.3V, if FPGA data setup time = 15 ns, then the actual TCYC = 25 ns +15 ns = 40 ns.
7.
Guaranteed by design; not tested.
8.
CF, EN_EXT_SEL, REV_SEL[1:0], and BUSY are inputs for the XCFxxP PROM only.
9.
When JTAG CONFIG command is issued, PROM drives CF Low for at least the THCF minimum.
Symbol
Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
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