參數資料
型號: XCB56364FU100
廠商: MOTOROLA INC
元件分類: 數字信號處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 8-BIT, 100 MHz, OTHER DSP, PQFP100
封裝: PLASTIC, TQFP-100
文件頁數: 74/162頁
文件大?。?/td> 2405K
代理商: XCB56364FU100
Specifications
Serial Host Interface (SHI) I
2
C Protocol Timing
2-54
DSP56364 Advance Information
MOTOROLA
2.12.1
Programming the Serial Clock
The programmed serial clock cycle, T
I
HCKR (SHI clock control register).
2
CCP
, is specified by the value of the HDM[5:0] and HRS bits of the
The expression for T
I
2
CCP
is
T
I
2
CCP
= [T
C
×
2
×
(HDM[7:0] + 1)
×
(7
×
(1 – HRS) + 1)]
where
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
— HDM[7:0] are the divider modulus select bits.
— A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.
186 First SCL sampling edge to
HREQ output deassertion
2
T
NG;RQO
ns
Filters bypassed
2
×
T
C
+ 30
50
50
Narrow filters enabled
2
×
T
C
+ 120
140
140
Wide filters enabled
2
×
T
C
+ 208
228
228
187 Last SCL edge to HREQ out-
put not deasserted
2
T
AS;RQO
ns
Filters bypassed
2
×
T
C
+ 30
50
50
Narrow filters enabled
2
×
T
C
+ 80
100
100
Wide filters enabled
2
×
T
C
+ 135
155
155
188 HREQ in assertion to first SCL
edge
T
AS;RQI
0.5
×
T
I
2
CCP
-
0.5
×
T
C
- 21
ns
Filters bypassed
4327
927
Narrow filters enabled
4282
882
Wide filters enabled
4238
838
R
P
(min) = 1.5 k
Table 2-18 SHI I
2
C Protocol Timing (continued)
Standard I
2
C*
No.
Characteristics
Symbol/
Expression
Standard-Mode
Fast-Mode
Unit
Min
Max
Min
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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