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參數(shù)資料
| 型號： | XC95288-15BG352I |
| 英文描述： | Flash Complex PLD |
| 中文描述： | 閃光復雜可編程邏輯器件 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 133K |
| 代理商： | XC95288-15BG352I |
R
XC9500 In-System Programmable CPLD Family
14
September 15, 1999 (Version 5.0)
Figure 15: Detailed Timing Model
Power-Up Characteristics
The XC9500 devices are well behaved under all operating
conditions. During power-up each XC9500 device employs
internal circuitry which keeps the device in the quiescent
state until the V
CCINT
supply voltage is at a safe level
(approximately 3.8 V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the IOB pull-up resistors (~ 10K ohms) enabled, as
shown in
Table 5
. When the supply voltage reaches a safe
level, all user registers become initialized (typically within
100
μ
s for 9536 - 95144, 200
μ
s for 95216 and 300
μ
s for
95288), and the device is immediately available for opera-
tion, as shown in
Figure 16
.
CoLogic
Propagation Delay = t
PD
(a)
CoLogic
Setup Time = t
SU
t
SU
t
PSU
t
PCO
t
CO
Clock to Out Time = t
CO
(b)
D/T
Q
Combinatorial
Logic
Internal System Cycle Time = t
SYSTEM
(d)
D/T
Q
Combinatorial
Logic
Combinatorial
Logic
Propagation Delay = t
PD +
t
FBK
With Feedback
(f)
Combinatorial
Logic
CoLogic
All resources within FB using local Feedback
Setup
Time
Internal Cycle Time = t
CNT
(e)
D/T
Q
Combinatorial
Logic
Setup Time = t
PSU
Clock to Out Time = t
PCO
(c)
P-Term Clock
Path
D/T
Q
Figure 14: Basic Timing Model
S*t
PTA
t
PTSR
t
PDI
t
SUI
t
HI
t
COI
t
AOI
t
RAI
SR
D/T
Q
>
t
IN
t
GCK
t
GSR
t
GTS
t
LOGILP
t
LOGI
t
PTCK
t
PTTS
t
LF
t
OUT
t
SLEW
t
EN
t
F
Pin Feedback
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| XC95288-15HQ208I | Flash Complex PLD |
| XC95288-20BG352C | Flash Complex PLD |
| XC95288XL-6BG352C | Flash Complex PLD |
| XC95288-20BG352I | Flash Complex PLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC95288-15BGG352C | 制造商:Xilinx 功能描述:XILINX XC95288-15BGG352C CPLD - Trays 制造商:Xilinx 功能描述:Xilinx XC95288-15BGG352C CPLD |
| XC95288-15BGG352I | 制造商:Xilinx 功能描述:XILINX XC95288-15BGG352I CPLD - Trays 制造商:Xilinx 功能描述:Xilinx XC95288-15BGG352I CPLD |
| XC95288-15HQ208C | 功能描述:IC CPLD SPEED GRADE 208-HQFP/COM RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC9528815HQ208I | 制造商:XILINX 功能描述:* |
| XC95288-15HQ208I | 功能描述:IC CPLD 288 MCELL I-TEMP 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
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