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參數(shù)資料
| 型號： | XC910C001DKSR |
| 廠商： | TOREX SEMICONDUCTOR LTD. |
| 英文描述： | PWM Controlled Step-Up DC/DC Controllers |
| 中文描述： | PWM控制升壓型DC / DC控制器 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 1058K |
| 代理商： | XC910C001DKSR |
12/22
XC9101
Series
5. FB Voltage and C
FB
With regard to the XC9101D series, the output voltage is set by attaching externally divided resistors. The output voltage
is determined by the equation shown below according to the values of R
FB1
and R
FB2
. In general, the sum of R
FB1
and
R
FB2
should be 1 M
Ω
or less.
V
OUT
= 0.9
×
(R
FB1
+ R
FB2
)/ R
FB2
The value of C
FB
(phase compensation capacitor) is approximated by the following equation according to the values of
R
FB1
and fzfb. The value of fzfb should be 10 kHz, as a general rule.
C
FB
= 1/(2
×
π
×
R
FB1
×
fzfb)
Example: When R
FB1
= 455 k
Ω
and R
FB2
= 100 k
Ω
:
V
OUT
= 0.9
×
(455 k
＋
100 k)/100 k = 4.995 V
:
C
FB
= 1/(2
×
π
×
455 k
×
10 k) = 34.98 pF
■
NOTES ON USE
●
Application Notes
1. The XC9101 series are designed for use with an output ceramic capacitor. If, however, the potential difference
between input and output is too large, a ceramic capacitor may fail to absorb the resulting high switching energy and
oscillation could occur on the output side. If the input-output potential difference is large, connect an electrolytic
capacitor in parallel to compensate for insufficient capacitance.
2. The EXT pin of the XC9101 series is designed to minimize the through current that occurs in the internal circuitry.
However, the gate drive of external PMOS has a low impedance for the sake of speed. Therefore, if the input voltage is
high and the bypass capacitor is attached away from the IC, the charge/discharge current to the external PMOS may
lead to unstable operations due to switching operation of the EXT pin.
As a solution to this problem, place the bypass capacitor as close to the IC as possible, so that voltage variations at the
V
IN
and V
SS
pins caused by switching are minimized. If this is not effective, insert a resistor of several to several tens
of ohms between the EXT pin and PMOS gate. Remember that the insertion of a resistor slows down the switching
speed and may result in reduced efficiency.
3. A NPN transistor can be used in place of PMOS. If using a PNP transistor, insert a resistor (R
B
) and capacitor (C
B
)
between the EXT pin and the base of the NPN transistor in order to limit the base current without slowing the switching
speed. Adjust R
B
in a range of 500
Ω
to 1 k
Ω
according to the load and hFE of the transistor. Use a ceramic
capacitor for C
B
, complying with
C
B
< 1/(2
×π×
R
B
×
FOSC
×
0.7)
, as a rule.
4. Although the C_CLK connection capacitance range is from 150 ~ 220pF, the most suitable value for maximum stability is
around 180pF.
■
OPERATIONAL EXPLANATION (Continued)
●
Functional Settings (Continued)
FB pin
Rfb1
Rfb2
Verr amplifier
0.9V
Cfb
Output voltage
Verr
V
IN
EXT pin
Rb
Cb
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