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| 型號： | XC6SLX100T-3FG484I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 23/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 484FGGBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB數(shù)： | 7911 |
| 邏輯元件/單元數(shù)： | 101261 |
| RAM 位總計： | 4939776 |
| 輸入/輸出數(shù)： | 296 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA |
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
3
Table 2: Recommended Operating Conditions(1)
Symbol
Description
Min
Typ
Max
Units
VCCINT
Internal supply voltage relative to GND
-3, -3N, -2
Standard performance(2)
1.14
1.2
1.26
V
-3, -2
Extended performance(2)
1.2
1.23
1.26
V
-1L
Standard performance(2)
0.95
1.0
1.05
V
VCCAUX(3)(4) Auxiliary supply voltage relative to GND
2.375
2.5
2.625
V
VCCAUX = 3.3V
3.15
3.3
3.45
V
VCCO(6)(7)(8) Output supply voltage relative to GND
1.1
–
3.45
V
VIN
Input voltage relative to GND
All I/O
standards
(except PCI)
Commercial temperature (C)
–0.5
–
4.0
V
Industrial temperature (I)
–0.5
–
3.95
V
Expanded (Q) temperature
–0.5
–
3.95
V
PCI I/O standard(9)
–0.5
–
VCCO +0.5
V
Maximum current through pin using PCI I/O standard
when forward biasing the clamp diode.(9)
Commercial (C) and
Industrial temperature (I)
––
10
mA
Expanded (Q) temperature
–
7
mA
VBATT(11)
Battery voltage relative to GND, Tj =0C to +85C
(LX75, LX75T, LX100, LX100T, LX150, and LX150T only)
1.0
–
3.6
V
Tj
Junction temperature operating range
Commercial (C) range
0
–
85
°C
Industrial temperature (I) range
–40
–
100
°C
Expanded (Q) temperature range
–40
–
125
°C
Notes:
1.
All voltages are relative to ground.
2.
See Interface Performances for Memory Interfaces in Table 25. The extended performance range is specified for designs not using the
standard VCCINT voltage range. The standard VCCINT voltage range is used for:
Designs that do not use an MCB
LX4 devices
Devices in the TQG144 or CPG196 packages
Devices with the -3N speed grade
3.
Recommended maximum voltage droop for VCCAUX is 10 mV/ms.
4.
During configuration, if VCCO_2 is 1.8V, then VCCAUX must be 2.5V.
5.
The -1L devices require VCCAUX = 2.5V when using the LVDS_25, LVDS_33, BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25,
and PPDS_33 I/O standards on inputs. LVPECL_33 is not supported in the -1L devices.
6.
Configuration data is retained even if VCCO drops to 0V.
7.
Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
8.
For PCI systems, the transmitter and receiver should have common supplies for VCCO.
9.
Devices with a -1L speed grade do not support Xilinx PCI IP.
10. Do not exceed a total of 100 mA per bank.
11. VBATT is required to maintain the battery backed RAM (BBR) AES key when VCCAUX is not applied. Once VCCAUX is applied, VBATT can be
unconnected. When BBR is not used, Xilinx recommends connecting to VCCAUX or GND. However, VBATT can be unconnected.
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