參數(shù)資料
型號(hào): XC61FN3852PH
廠商: TOREX SEMICONDUCTOR LTD.
英文描述: Voltage Detectors ( Delay Circuit Built-In)
中文描述: 電壓檢測(cè)器(延遲電路內(nèi)置)
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 204K
代理商: XC61FN3852PH
163
2
G
Functional Description ( CMOS output )
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t
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When a voltage higher than the release voltage (V
DR
) is applied to the voltage input pin (V
IN
), the voltage will gradually fall.
When a voltage higher than the detect voltage (V
DF
) is applied to V
IN
, output (V
OUT
) will be equal to the input at V
IN
.
Note that high impedeance exists at V
OUT
with the N-channel open drain configuration. If the pin is pulled up, V
OUT
will be
equal to the pull up voltage.
When V
IN
falls below V
DF
, V
OUT
will be equal to the ground voltage (V
SS
) level (detect state).
Note that this also applies to N-channel open drain configurations.
When V
IN
falls to a level below that of the minimum operating voltage (V
MIN
) output will become unstable.
Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), V
OUT
will be equal to V
SS
until
V
IN
reaches the V
DR
level.
Although V
IN
will rise to a level higher than V
DR
, V
OUT
maintains ground voltage level via the delay circuit.
Following transient delay time, V
IN
will be output at V
OUT
.
Note that high impedeance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
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Notes :
1.
2.
The difference between V
DR
and V
DF
represents the hysteresis range.
Propagation delay time (tDLY) represents the time it takes for V
IN
to appear at V
OUT
once the said voltage has exceeded the
V
DR
level.
Input Voltage
(V
IN
)
Minimum Operating Voltage
(
V
MIN
)
Detect Release Voltage (V
DR
)
Detect Voltage
(V
DF
)
Output Voltage (V
OUT
)
Ground Voltage (V
SS
)
Ground Voltage (V
SS
)
Propagation Delay Time (tDLY)
G
Timing Chart
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