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鍨嬭櫉(h脿o)锛� XC5VLX85-1FFG1153I
寤犲晢锛� Xilinx Inc
鏂囦欢闋佹暩(sh霉)锛� 74/91闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA VIRTEX-5 85K 1153FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� Virtex®-5 LX
LAB/CLB鏁�(sh霉)锛� 6480
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 82944
RAM 浣嶇附瑷�(j矛)锛� 3538944
杓稿叆/杓稿嚭鏁�(sh霉)锛� 560
闆绘簮闆诲锛� 0.95 V ~ 1.05 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 1153-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1153-FCBGA锛�35x35锛�
閰嶇敤锛� 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
76
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC5VTX150T
N/A
1.82
鈥�0.56
1.95
鈥�0.56
ns
XC5VTX240T
N/A
2.05
鈥�0.43
2.26
鈥�0.43
ns
XC5VFX30T
1.82
鈥�0.40
1.93
鈥�0.40
2.09
鈥�0.40
ns
XC5VFX70T
1.79
鈥�0.30
1.90
鈥�0.30
2.07
鈥�0.30
ns
XC5VFX100T
1.81
鈥�0.43
1.91
鈥�0.40
2.09
鈥�0.38
ns
XC5VFX130T
1.79
鈥�0.29
1.95
鈥�0.28
2.14
鈥�0.24
ns
XC5VFX200T
N/A
2.06
鈥�0.14
2.29
鈥�0.14
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2.
IFF = Input Flip-Flop or Latch.
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 94: Global Clock Setup and Hold With PLL in System-Synchronous Mode (Cont鈥檇)
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
鐩搁棞(gu膩n)PDF璩囨枡
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EMC18DTEH CONN EDGECARD 36POS .100 EYELET
XC5VFX70T-1FFG1136I IC FPGA VIRTEX-5FX 70K 1136-FBGA
EMC17DTEF CONN EDGECARD 34POS .100 EYELET
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