鍨嬭櫉(h脿o)锛� | XC5VLX85-1FFG1153I |
寤犲晢锛� | Xilinx Inc |
鏂囦欢闋佹暩(sh霉)锛� | 74/91闋� |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC FPGA VIRTEX-5 85K 1153FBGA |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
绯诲垪锛� | Virtex®-5 LX |
LAB/CLB鏁�(sh霉)锛� | 6480 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 82944 |
RAM 浣嶇附瑷�(j矛)锛� | 3538944 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 560 |
闆绘簮闆诲锛� | 0.95 V ~ 1.05 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | -40°C ~ 100°C |
灏佽/澶栨锛� | 1153-BBGA锛孎(xi脿n)CBGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 1153-FCBGA锛�35x35锛� |
閰嶇敤锛� | 568-5088-ND - BOARD DEMO DAC1408D750 |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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XC5VLX85-1FF1153I | IC FPGA VIRTEX-5 85K 1153FBGA |
EMC18DTEN | CONN EDGECARD 36POS .100 EYELET |
EMC18DTEH | CONN EDGECARD 36POS .100 EYELET |
XC5VFX70T-1FFG1136I | IC FPGA VIRTEX-5FX 70K 1136-FBGA |
EMC17DTEF | CONN EDGECARD 34POS .100 EYELET |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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XC5VLX85-1FFG676C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 85K 676FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX85-1FFG676CES | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 ES 85K 676-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Kintex-7 LAB/CLB鏁�(sh霉):25475 閭忚集鍏冧欢/鍠厓鏁�(sh霉):326080 RAM 浣嶇附瑷�(j矛):16404480 杓稿叆/杓稿嚭鏁�(sh霉):350 闁€鏁�(sh霉):- 闆绘簮闆诲:0.97 V ~ 1.03 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:900-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:900-FCBGA锛�31x31锛� 鍏跺畠鍚嶇ū:122-1789 |
XC5VLX85-1FFG676I | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 85K 676FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX85-2FF1153C | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 85K 1153FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:Step Intro and Pkg Change 11/March/2008 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:Virtex®-5 SXT LAB/CLB鏁�(sh霉):4080 閭忚集鍏冧欢/鍠厓鏁�(sh霉):52224 RAM 浣嶇附瑷�(j矛):4866048 杓稿叆/杓稿嚭鏁�(sh霉):480 闁€鏁�(sh霉):- 闆绘簮闆诲:0.95 V ~ 1.05 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:1136-BBGA锛孎(xi脿n)CBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:1136-FCBGA 閰嶇敤:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
XC5VLX85-2FF1153I | 鍔熻兘鎻忚堪:IC FPGA VIRTEX-5 85K 1153FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Virtex®-5 LX 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:XC4000(E,L) Discontinuation 01/April/2002 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:XC4000E/X LAB/CLB鏁�(sh霉):100 閭忚集鍏冧欢/鍠厓鏁�(sh霉):238 RAM 浣嶇附瑷�(j矛):3200 杓稿叆/杓稿嚭鏁�(sh霉):80 闁€鏁�(sh霉):3000 闆绘簮闆诲:4.5 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:120-BCBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:120-CPGA锛�34.55x34.55锛� |