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參數(shù)資料
型號: XC5VLX330-1FFG1760I
廠商: Xilinx Inc
文件頁數(shù): 72/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 330K 1760FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 25920
邏輯元件/單元數(shù): 331776
RAM 位總計: 10616832
輸入/輸出數(shù): 1200
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML525-UNI-G-ND - EVAL PLATFORM ROCKET IO VIRTEX-5
HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
74
TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in
Source-Synchronous Mode
XC5VTX150T
N/A
0.25
0.97
0.25
1.03
ns
XC5VTX240T
N/A
0.24
1.20
0.24
1.26
ns
XC5VFX30T
0.16
0.91
0.18
0.95
0.19
1.01
ns
XC5VFX70T
0.13
0.83
0.14
0.86
0.14
0.92
ns
XC5VFX100T
0.21
0.98
0.21
1.00
0.21
1.05
ns
XC5VFX130T
0.19
1.15
0.21
1.19
0.24
1.25
ns
XC5VFX200T
N/A
0.14
1.50
0.16
1.55
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2.
IFF = Input Flip-Flop or Latch
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 93: Global Clock Setup and Hold With DCM in Source-Synchronous Mode (Cont’d)
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
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