參數(shù)資料
型號(hào): XC4VLX40-10FFG668C
廠商: Xilinx Inc
文件頁數(shù): 31/58頁
文件大小: 0K
描述: IC FPGA VIRTEX-4 40K 668-FCBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-4 LX
LAB/CLB數(shù): 4608
邏輯元件/單元數(shù): 41472
RAM 位總計(jì): 1769472
輸入/輸出數(shù): 448
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 668-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 668-FCBGA
配用: HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
其它名稱: 122-1492
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
37
Boundary-Scan Port Timing Specifications
TTAPTCK
TMS and TDI Setup time before TCK
1.0
ns, Min
TTCKTAP
TMS and TDI Hold time after TCK
2.0
ns, Min
TTCKTDO
TCK falling edge to TDO output valid
6.0
ns, Max
FTCK
Maximum configuration TCK clock
frequency
66
MHz, Max
FTCKB
Maximum Boundary-Scan TCK clock
frequency
50
MHz, Max
Dynamic Reconfiguration Port (DRP) for DCM
CLKIN_FREQ_DLL_HF_MS_MAX
Maximum frequency for DCLK
500
450
400
MHz, Max
TDMCCK_DADDR/TDMCKC_DADDR
DADDR Setup/Hold time
0.54
0.00
0.63
0.00
0.72
0.00
ns, Max
TDMCCK_DI/TDMCKC_DI
DI Setup/Hold time
0.54
0.00
0.63
0.00
0.72
0.00
ns, Max
TDMCCK_DEN/TDMCKC_DEN
DEN Setup/Hold time
0.58
0.00
0.58
0.00
0.58
0.00
ns, Max
TDMCCK_DWE/TDMCKC_DWE
DWE Setup/Hold time
0.58
0.00
0.58
0.00
0.58
0.00
ns, Max
TDMCKO_DO
CLK to out of DO(2)
00
0
ns, Max
TDMCKO_DRDY
CLK to out of DRDY
0.68
0.80
0.92
ns, Max
Notes:
1.
TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters
do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only
needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
2.
DO holds until the next DRP operation.
Table 43: Configuration Switching Characteristics (Continued)
Symbol
Description
Speed Grade
Units
-12
-11
-10
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