參數(shù)資料
型號(hào)： XC4VLX15-11FFG676I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 1536 CLBS, 1205 MHz, PBGA676
封裝： LEAD FREE, FBGA-676
文件頁數(shù)： 3/58頁
文件大小： 1863K
代理商： XC4VLX15-11FFG676I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
11
RocketIO DC Input and Output Levels
Table 12 summarizes the DC input and output specifica-
tions of the Virtex-4 FPGA RocketIO Multi-Gigabit Serial
Transceivers. Figure 1 shows the single-ended output volt-
age swing. Figure 2 shows the peak-to-peak differential out-
put voltage. Consult the Virtex-4 RocketIO Multi-Gigabit
Transceiver User Guide for further details.
Table 12: RocketIO DC Specifications
DC Parameter
Symbol
Conditions
Min
Typ
Max
Units
Peak-to-Peak Differential Input Voltage
DVIN
Internal AC Coupled
110
2400
mV
Single-Ended Input Range
SEVIN
Internal AC Coupled
0
VTRX
mV
Common Mode Input Voltage Range
VICM
Internal AC Coupled
100
VTRX –100
mV
Bypassed Internal AC
Coupled (1)
800
mV
Single-Ended Output Voltage Swing(2, 3)
VOUT
450
725
mV
Common Mode Output Voltage Range(3)
VTCM
1000
mV
Peak-to-Peak Differential Output Voltage(2, 3)
DVPPOUT
900
1050
1400
mV
Signal detect threshold
RXOOBVDPP
RX
TBD
Electrical idle amplitude
TXOOBVDPP
TX
65
mV
RocketIO MGT Clock DC Input Levels
Peak-to-Peak Differential Input Voltage
VIDIFF
2 x | VMGTCLKP – VMGTCKLN |
100
600
2000
mV
Differential Input Resistance
RIN
71
105
124
Ω
Notes:
1.
The maximum VTRX is 1.26V when bypassing the internal AC coupled VICM. VTRX must be less than or equal to AVCCAUXRX.
2.
The output swing and pre-emphasis levels are selected using the attributes discussed in Chapter 4: PMA Analog Considerations in the Virtex-4
3.
VTTX is 1.5 ± 5%; different amplitudes possible with adjusted DAC values.
Figure 1: Single-Ended Output Voltage Swing
Figure 2: Peak-to-Peak Differential Output Voltage
0
+V
TXP
TXN
DVOUT
DS302_02_031708
0
+V
–V
TXP–TXN
DVPPOUT
DS302_03_031708
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