參數(shù)資料
型號(hào)： XC4VFX12-11FFG668C
廠商： Xilinx Inc
文件頁數(shù)： 5/58頁
文件大小： 0K
描述： IC FPGA VIRTEX-4 FX 12K 668FCBGA
標(biāo)準(zhǔn)包裝： 40
系列： Virtex®-4 FX
LAB/CLB數(shù)： 1368
邏輯元件/單元數(shù)： 12312
RAM 位總計(jì)： 663552
輸入/輸出數(shù)： 320
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 668-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 668-FCBGA
配用： HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
13
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotate to the
simulation net list. Unless otherwise noted, values apply to
all Virtex-4 devices.
PowerPC Switching Characteristics
Consult the PowerPC 405 Processor Block Reference Guide for further information.
Table 15: PowerPC 405 Processor Clocks Absolute AC Characteristics
Description
Speed Grade
Units
-12
-11
-10
MinMax
Characteristics when APU Not Used
CPMC405CLOCK frequency(1,4)
0450
0400
0350
MHz
CPMDCRCLK(3)
0450
0400
0350
MHz
CPMFCMCLK(3)
NA
MHz
JTAGC405TCK frequency(2)
0225
0200
0175
MHz
PLBCLK(3)
0450
0400
0350
MHz
BRAMDSOCMCLK(3)
0450
0400
0350
MHz
BRAMISOCMCLK(3)
0450
0400
0350
MHz
Characteristics when APU Used
CPMC405CLOCK frequency(1,4)
0333
0275
0233
MHz
CPMDCRCLK(3)
0333
0275
0233
MHz
CPMFCMCLK(3)
0333
0275
0233
MHz
JTAGC405TCK frequency(2)
0166.5
0137.5
0116.5
MHz
PLBCLK(3)
0333
0275
0233
MHz
BRAMDSOCMCLK(3)
0333
0275
0233
MHz
BRAMISOCMCLK(3)
0333
0275
0233
MHz
Notes:
1.
Worst-case DCM output clock jitter is included in these specifications.
2.
The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will
be much less.
3.
The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and
BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and
CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent.
4.
Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.
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