參數(shù)資料
型號(hào)： XC4028XLA
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 72K
代理商： XC4028XLA
R
XC4000XLA/XV FIeld Programmable Gate Arrays
6-180
DS004 (v. 1.3) October 4, 1999 - Product Specification
XC4000XLA Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Global Low Skew Clock, Set-Up and Hold
Speed Grade
Device
-09
Min
-08
Min
-07
Min
Units
Description
Symbol
Input Setup and Hold Time Relative to Global Clock Input Signal
No Delay
Global Low Skew Clock and IFF
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
1.0 / 3.0
0.9 / 3.2
0.8 / 3.8
0.6 / 4.0
0.4 / 4.4
0.3 / 4.6
0.2 / 5.0
0.0 / 5.4
4.4 / 0.5
4.5 / 0.6
4.6 / 0.7
4.6 / 0.8
4.7 / 0.9
4.8 / 1.0
5.0 / 1.0
5.5 / 1.2
4.4 / 0.0
4.6 / 0.0
4.8 / 0.0
4.9 / 0.0
5.0 / 0.0
5.2 / 0.0
5.5 / 0.0
6.0 / 0.0
0.8 / 2.6
0.7 / 2.9
0.6 / 3.3
0.4 / 3.5
0.2 / 3.9
0.2 / 4.1
0.1 / 4.5
0.0 / 4.8
4.1 / 0.3
4.1 / 0.3
4.2 / 0.4
4.2 / 0.4
4.3 / 0.5
4.3 / 0.6
4.4 / 0.7
4.7 / 0.9
4.1 / 0.0
4.2 / 0.0
4.4 / 0.0
4.5 / 0.0
4.6 / 0.0
4.7 / 0.0
4.9 / 0.0
5.2/ 0.0
Preliminary
0.2 / 2.5
0.1 / 2.7
0.0 / 3.0
0.0 / 3.3
0.0 / 3.6
0.0 / 3.9
0.0 / 4.2
0.0 / 4.5
3.7/ 0.0
3.7 / 0.0
3.7/ 0.0
3.7/ 0.0
3.8 / 0.0
3.8 / 0.2
3.8 / 0.4
3.8 / 0.5
3.7 / 0.0
3.8 / 0.0
3.9 / 0.0
4.0 / 0.0
4.1 / 0.0
4.2 / 0.0
4.3 / 0.0
4.4 / 0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
PSN
/T
PHN
Partial Delay
Global Low Skew Clock and IFF
T
PSP
/T
PHP
Full Delay
Global Low Skew Clock and IFF
T
PSD
/T
PHD
IFF = Input Flip-Flop or Latch
Note:
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is
measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two
IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions.
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