參數(shù)資料
型號(hào)： XC4028XLA-09HQ240I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 2/14頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I 2.5V 256 I/O 240HQFP
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 24
系列： XC4000XLA/XV
LAB/CLB數(shù)： 1024
邏輯元件/單元數(shù)： 2432
RAM 位總計(jì)： 32768
輸入/輸出數(shù)： 193
門數(shù)： 28000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 240-PQFP（32x32）
其它名稱： Q1143124
XC4028XLA09HQ240I
R
XC4000XLA/XV Field Programmable Gate Arrays
6-166
DS015 (v2.0) March 1, 2013 - Product Specification
Product Obsolete/Under Obsolescence
Data Stream Format
The data stream (“bitstream”) format is identical for all
serial
configuration
modes,
but
different
for
the
4000XLA/XV Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no
length count is required. Additionally, CRC error checking is
not supported in Express mode. The data stream format is
shown in Table 9. Express mode data is shown with D0 at
the left and D7 at the right.
The configuration data stream begins with two bytes of
eight ones each, a preamble code of one byte, followed by
three bytes of eight ones each, and finally an end-of-
header field check byte. This header of seven bytes is fol-
lowed by the actual configuration data in frames. The length
and number of frames depends on the device type. Each
frame begins with a start field and ends with an
end-of-frame field check byte. In all cases, additional
start-up bytes of data are required to provide six, or more,
clocks for the start-up sequence at the end of configuration.
Long daisy chains require additional startup bytes to shift
the last data through the chain. All startup bytes are
don’t-cares; these bytes are not included in bitstreams cre-
ated by the Xilinx software.
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The 4000XLA
Express mode only supports non-CRC error checking. The
non-CRC
error
checking
tests
for
a
designated
end-of-frame field check byte for each frame. non-CRC
error checking tests for a designated end-of-frame field
check byte for each frame.
LEGEND:
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. The user must
detect INIT and initialize a new configuration by pulsing the
PROGRAM pin Low or cycling VCC.
Note: CS1 must remain High throughout loading of the configuration data stream. In the pseudo daisy chain of Figure 5, the 7 byte
data stream header is loaded into all devices simultaneously. Each device’s data frames are then loaded in turn when its
CS1 pin is driven High by the DOUT of the preceding device in the chain.
99012600
BYTE
0
CCLK
1
2
3
INIT
T
DC
T
CD
T
IC
D0-D7
DOUT
CS1
First
FPGA
BYTE
1
BYTE
2
BYTE
3
First FPGA Filled
BYTE
4
BYTE
5
BYTE
6
Header
Header Loaded
CS1
Second
FPGA
CS1 all
downstream
FPGAs
Byte A is first frame byte for first FPGA
Byte B is last frame byte for first FPGA
Byte C is first frame byte for second FPGA
BYTE
A
BYTE
C
BYTE
B
Figure 6: Express Mode Configuration Switching Waveforms
Table 9: 4000XLA/XV Express Mode Data Stream
Format
Data Type
Express Mode
(D0-D7)
(4000XLA only)
Fill Byte
FFFFh
Preamble Code
11110010b
Fill Byte
FFFFFFh
End-of-Header
Field Check Byte
11010010b
Start Field
11111110b
Data Frame
DATA(n-1:0)
End-of-Frame
Field Check Byte
11010010b
Extend Write Cycle
FFD2FFFFFFh
Start-Up Bytes
FFFFFFFFFFFFh
Unshaded
Once per data stream
Light
Once per data frame
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