- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4258 > XC3SD3400A-5FGG676C (Xilinx Inc)SPARTAN-3ADSP FPGA 3400K 676FBGA PDF資料下載
參數(shù)資料
| 型號： | XC3SD3400A-5FGG676C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 676FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Spartan®-3A DSP |
| LAB/CLB數(shù)： | 5968 |
| 邏輯元件/單元數(shù)： | 53712 |
| RAM 位總計： | 2322432 |
| 輸入/輸出數(shù)： | 469 |
| 門數(shù)： | 3400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
| 配用： | 122-1532-ND - KIT DEVELOPMENT SPARTAN 3ADSP |
Extended Spartan-3A Family Overview
DS706 (v1.1) February 2, 2011
Product Specification
3
R
Architectural Overview
The Extended Spartan-3A family architecture consists of
five fundamental programmable functional elements:
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier or DSP48A Blocks accept two 18-bit binary
numbers as inputs and calculate the product. The
DSP48A blocks in the two largest members of the
Extended Spartan-3A family add an 18-bit pre-adder
and 48-bit accumulator.
Digital Clock Manager (DCM) Blocks provide self-
calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
Configuration
The Extended Spartan-3A family is programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA
configuration data is stored externally in a PROM or some
other nonvolatile medium, either on or off the board, or
stored within the FPGA in the nonvolatile Spartan-3AN
devices. After applying power, the configuration data is
written to the FPGA using any of eight different modes:
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an industry-
standard SPI serial flash
Internal SPI flash memory (Spartan-3AN devices)
Byte Peripheral Interface (BPI) Up from an industry-
standard x8 or x8/x16 parallel NOR flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
MultiBoot configuration
MultiBoot configuration allows two or more FPGA
configuration bitstreams to be stored in a single SPI serial
flash or a parallel NOR flash. The FPGA application controls
which configuration to load next and when to load it.
Additionally, each FPGA in the Extended Spartan-3A family
contains a unique, factory-programmed Device DNA
identifier useful for tracking purposes, anti-cloning designs,
or IP protection.
I/O Capabilities
The SelectIO interface of the Extended Spartan-3A family
supports many popular single-ended and differential
standards. Table 2 shows the maximum number of user
I/Os and input-only pins for each device/package
combination.
FPGAs in the Extended Spartan-3A family support the
following single-ended standards:
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
FPGAs in the Extended Spartan-3A family support the
following differential standards:
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 25LC160BT-E/ST | IC EEPROM 16KBIT 10MHZ 8TSSOP |
| XC3S1600E-4FGG484I | IC FPGA SPARTAN-3E 1600K 484FBGA |
| 25LC160B-E/MS | IC EEPROM 16KBIT 10MHZ 8MSOP |
| 25LC160AT-E/ST | IC EEPROM 16KBIT 10MHZ 8TSSOP |
| 25LC160AT-E/MS | IC EEPROM 16KBIT 10MHZ 8MSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC40 DO NOT USE## | 制造商:Xilinx 功能描述: |
| XC40 DO NOT USE### | 制造商:Xilinx 功能描述: |
| XC40 DO NOT USE##### | 制造商:Xilinx 功能描述: |
| XC40 DO NOT USE###### | 制造商:Xilinx 功能描述: |
| XC40 DO NOT USE#1# | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。