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參數(shù)資料
| 型號： | XC3190L-3TQ144C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 320 CLBS, 5000 GATES, 270 MHz, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 61/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3190L-3TQ144C |
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R
November 9, 1998 (Version 3.1)
7-63
XC3000 Series Field Programmable Gate Arrays
7
XC3100L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
Speed Grade
Symbol
-3
-2
Description
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch (XC3100L)
transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
3
4
T
PID
T
PTG
T
IKRI
2.2
11.0
2.2
2.0
11.0
1.9
ns
ns
ns
XC3142L
XC3190L
1
T
PICK
9.5
9.9
9.0
9.4
ns
ns
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z
same
3-state to Pad active and valid(fast)(XC3100L)
same
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time (XC3100L)
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Export Control Maximum flip-flop toggle rate
Global Reset Delays
RESET Pad to Registered In (Q)
(fast)
(slew rate limited)
(fast)
(slew-rate limited)(XC3100L)
(fast)
(slew-rate limited)
(slew -rate limited)
7
7
10
10
9
9
8
8
T
OKPO
T
OK
PO
T
OPF
T
OPF
T
TSHZ
T
TSHZ
T
TSON
T
TSON
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
4.0
9.7
3.0
8.7
5.0
5.0
8.5
14.2
ns
ns
ns
ns
ns
ns
ns
ns
5
6
T
OOK
T
OKO
4.0
0
3.6
0
ns
ns
11
12
T
IOH
T
IOL
F
TOG
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
(XC3142L)
(XC3190L)
(fast)
(slew-rate limited)
RESET Pad to output pad
13
15
15
T
RRI
T
RPO
T
RPO
16.0
21.0
17.0
23.0
16.0
21.0
17.0
23.0
ns
ns
ns
ns
Advance
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