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參數(shù)資料
| 型號： | XC3142A-3VQ100C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 144 CLBS, 2000 GATES, 270 MHz, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁數(shù)： | 8/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3142A-3VQ100C |
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-110
Figure 5
5a.
Combinatorial Logic Option FG generates two functions
of four variables each. One variable, A, must be common
to both functions. The second and third variable can be
any choice of of B, C, QX and QY The fourth variable
can be any choice of D or E.
5b.
Combinatorial Logic Option F generates any function of
five variables: A, D, E and and two choices out of B, C,
QX, QY.
5c.
Combinatorial Logic Option FGM allows variable E to
select between two functions of four variables: Both have
common inputs A and D and any choice out of B, C, QX
and QY for the remaining two variables. Option 3 can
then implement some functions of six or seven variables.
QY
Any Function
of Up to 4
Variables
QY
Any Function
of Up to 4
Variables
QY
Any Function
of 5 Variables
QY
Any Function
of Up to 4
Variables
QY
Any Function
of Up to 4
Variables
5c
5b
5a
QX
QX
QX
QX
QX
A
B
C
D
A
B
C
D
E
E
A
B
C
D
E
D
A
B
C
D
C
A
B
M
U
X
F
G
F
G
F
G
E
X5442
FGM
Mode
D
Q
D
Q
D
Q
Count Enable
Parallel Enable
Clock
D2
D1
D0
Dual Function of 4 Variables
Function of 6 Variables
Function of 5 Variables
Q2
Q1
Q0
FG
Mode
F
Mode
FGM
Mode
Terminal
Count
X5383
Figure 6.
C8BCP Macro.
The C8BCP macro
(modulo-8 binary counter with parallel
enable and clock enable) uses one combinatorial logic block
of each option.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC3142A-3VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3142A-4PC84C | 制造商:Xilinx 功能描述:CMOS FPGA SMD 3142 PLCC84 5.25V |
| XC3142A-4PC84C0100 | 制造商:Xilinx 功能描述: |
| XC3142A-4PC84I | 制造商:Xilinx 功能描述: |
| XC3142A-4PCG84 | 制造商:Xilinx 功能描述:CMOS FPGA SMD 3142 PLCC84 5.25V |
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