參數(shù)資料
型號(hào)： XC3100
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Families
中文描述： 家庭邏輯單元陣列
文件頁(yè)數(shù)： 14/50頁(yè)
文件大小： 474K
代理商： XC3100
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-116
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND func-
tion. A logic High on both buffer inputs creates a high
impedance, which represents no contention. A logic Low
enables the buffer to drive the Longline Low. See Figure
15b. Pull-up resistors are available at each end of the
Longline to provide a High output when all connected
buffers are non-conducting. This forms fast, wide gating
functions. When data drives the inputs, and separate
signals drive the 3-state control lines, these buffers form
multiplexers (3-state busses). In this case, care must be
used to prevent contention through multiple active buffers
Figure 14
.
Programmable Interconnection of Longlines.
This is provided at the edges of the routing area. Three-state buffers
allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines
per column (except XC3020) and the outer perimeter Longlines may be programmed as connectible half-length lines.
X1244
X1741
D
A
A
D
B
B
D
C
C
D
N
N
D
A
A
+
=
D
B
B
+ D
C
C
+
D
N
N
Z
… +
WEAK
KEEPER
CIRCUIT
Figure 15b.
3-State Buffers Implement a Multiplexer.
The selection is accomplished by the buffer 3-state signal.
V
CC
D
A
D
B
D
C
D
N
V
CC
Z
=
D
A
D
B
D
C
...
D
N
X3036
(LOW)
T
OE
Figure 15a
.
3-State Buffers Implement a Wired-AND Function.
When all the buffer 3-state
lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer
inputs are driven by the control signals or a Low.
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