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| 型號(hào)： | XC3064L-8TQ144I |
| 廠(chǎng)商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 224 CLBS, 3500 GATES, 80 MHz, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 52/76頁(yè) |
| 文件大小： | 731K |
| 代理商： | XC3064L-8TQ144I |
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R
XC3000 Series Field Programmable Gate Arrays
7-54
November 9, 1998 (Version 3.1)
XC3100A Absolute Maximum Ratings
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3100A Global Buffer Switching Characteristics Guidelines
Note:
1. Timing is based on the XC3142A, for other devices see timing calculator.
The use of two pull-up resistors per longline, available on other XC3000 devices, is not a valid design option for XC3100A
devices.
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
Description
Units
V
V
V
°
C
°
C
°
C
°
C
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
Junction temperature plastic
Junction temperature ceramic
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–65 to +150
+260
+125
+150
T
J
Speed Grade
Symbol
-4
-3
-2
-1
-09
Max
Description
Max
Max
Max
Max
Units
Global and Alternate Clock Distribution
1
Either:
Normal
IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast
(CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF
driving a Horizontal Longline (L.L.)
1
I to L.L. while T is Low (buffer active)
T
PID
T
PIDC
6.5
5.1
5.6
4.3
4.7
3.7
4.3
3.5
3.9
3.1
ns
ns
(XC3100)
(XC3100A)
T
↓
to L.L. active and valid with single pull-up resistor
T
↓
to L.L. active and valid with pair of pull-up resistors
T
↑
to L.L. High with single pull-up resistor
T
↑
to L.L. High with pair of pull-up resistors
T
IO
T
IO
T
ON
T
ON
T
PUS
T
PUF
3.7
3.6
5.0
6.5
13.5
10.5
3.1
3.1
4.2
5.7
11.4
8.8
3.1
4.2
5.7
11.4
8.1
2.9
4.0
5.5
10.4
7.1
2.1
3.1
4.6
8.9
5.9
ns
ns
ns
ns
ns
ns
BIDI
Bidirectional buffer delay
T
BIDI
1.2
1.0
0.9
0.85
0.75
Prelim
ns
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