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| 型號： | XC3064L-8PC84I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 224 CLBS, 3500 GATES, 80 MHz, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 28/76頁 |
| 文件大小： | 731K |
| 代理商： | XC3064L-8PC84I |
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R
XC3000 Series Field Programmable Gate Arrays
7-30
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, V
must rise from 2.0 V to V
min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
rise time of >100 ms, or a
non-monotonically rising V
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low level on RESET and D/P
after V
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. T
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
BUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
Note:
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY
will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted
immediately after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics
6
BUSY
T
D6
DOUT
RDY/BUSY
D7
D0
D1
D2
4
WTRB
T
Valid
2
DC
T
1
CA
T
CCLK
D0-D7
CS2
WS, CS0, CS1
3
CD
T
WRITE TO FPGA
X5992
Previous Byte
New Byte
Description
Symbol
Min
100
Max
Units
ns
WRITE
Effective Write time required
(Assertion of CS0, CS1, CS2, WS)
DIN Setup time required
DIN Hold time required
RDY/BUSY delay after end of WS
1
T
CA
2
3
4
T
DC
T
CD
T
WTRB
60
0
ns
ns
ns
60
RDY
Earliest next WS after end of BUSY
5
T
RBWT
0
ns
BUSY Low time generated
6
T
BUSY
2.5
9
CCLK
periods
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