參數(shù)資料
型號： XC3030L-8PC84C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 100 CLBS, 1500 GATES, 80 MHz, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 47/76頁
文件大?。?/td> 731K
代理商： XC3030L-8PC84C
R
November 9, 1998 (Version 3.1)
7-49
XC3000 Series Field Programmable Gate Arrays
7
XC3000L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. Timing is based on the XC3042L, for other devices see timing calculator.
2. The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
Speed Grade
Symbol
-8
Description
Min
Max
Units
Combinatorial Delay
Logic Variables
A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
1
T
ILO
6.7
7.5
ns
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG Mode
F and FGM Mode
Data In
DI
Enable Clock
EC
Hold Time after clock K
Logic Variables
A, B, C, D, E
Data In
DI
2
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)
1
RESET width (Low)
delay from RESET pad to outputs X or Y
8
T
CKO
T
QLO
7.5
14.0
14.8
ns
ns
ns
2
4
6
T
ICK
T
DICK
T
ECCK
5.0
5.8
5.0
6.0
ns
ns
ns
ns
3
5
7
T
CKI
T
CKDI
T
CKEC
0
2.0
2.0
ns
ns
ns
11
12
T
CH
T
CL
F
CLK
5.0
5.0
80.0
ns
ns
MHz
13
9
T
RPW
T
RIO
7.0
7.0
ns
ns
T
MRW
T
MRQ
16.0
23.0
ns
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3030L-8PC84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030L-8VQ100C 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030L-8VQ100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030L-8VQ64C 功能描述:IC FPGA C-TEMP 3.3V 64-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3030L-8VQ64I 功能描述:IC FPGA I-TEMP 3.3V 64-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
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