參數(shù)資料
型號(hào)： XC3030A-7PC84C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 18/76頁(yè)
文件大?。?/td> 0K
描述： IC LOGIC CL ARRAY 3000GAT 84PLCC
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC3000A/L
LAB/CLB數(shù)： 100
RAM 位總計(jì)： 22176
輸入/輸出數(shù)： 74
門(mén)數(shù)： 2000
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線(xiàn)）
供應(yīng)商設(shè)備封裝： 84-PLCC
其它名稱(chēng)： 122-1018
R
November 9, 1998 (Version 3.1)
7-27
XC3000 Series Field Programmable Gate Arrays
7
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead device) on the DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
X5990
RCLK
General-
Purpose
User I/O
Pins
M0 M1PWRDWN
M2
HDC
Other
I/O Pins
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
+5 V
.....
CE
OE
FPGA
CCLK
DOUT
System Reset
A11
A12
A13
A14
A15
EPROM
RESET
...
Other
I/O Pins
DOUT
M2
HDC
LDC
FPGA
Slave #1
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
Reset
DOUT
FPGA
Slave #n
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
General-
Purpose
User I/O
Pins
RESET
Master
...
+5 V
8
INIT
...
M2
HDC
LDC
INIT
General-
Purpose
User I/O
Pins
+5 V
D/P
Other
I/O Pins
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
Open
Collector
INIT
N.C.
Reprogram
5 k
5 k
5 k
5 k
Each
If Readback is
Activated, a
5-k
Resistor is
Required in
Series With M1
*
**
Figure 25: Master Parallel Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
AGM43DTMS-S189 CONN EDGECARD 86POS R/A .156 SLD
AYM43DTBS-S189 CONN EDGECARD 86POS R/A .156 SLD
ASM43DTBS-S189 CONN EDGECARD 86POS R/A .156 SLD
A14V25A-VQG100C IC FPGA 2500 GATES 3.3V 100-VQFP
A14V25A-VQ100C IC FPGA 2500 GATES 3.3V 100-VQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3030A-7PC84C0100 制造商:Xilinx 功能描述:
XC3030A-7PC84I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030A-7PQ100C 功能描述:IC LOGIC CL ARRAY 3000GAT 100PQF RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3030A-7PQ100I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030A-7VQ100C 制造商:Xilinx 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*