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參數(shù)資料
| 型號： | XC3030A-7PC44C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 100 CLBS, 1500 GATES, 113 MHz, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3030A-7PC44C |
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R
November 9, 1998 (Version 3.1)
7-55
XC3000 Series Field Programmable Gate Arrays
7
XC3100A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (T
, #5) of any CLB on the same die.
2. T
, T
and T
are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100A family increases by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3), 0.35 ns (-2), 0.30 ns (-1), and
0.30 ns (-09).
Speed Grade
Symbol
-4
-3
-2
-1
-09
Description
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Combinatorial Delay
Logic Variables
to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive
X or Y
Set-up time before clock K
Logic Variables
Data In
Enable Clock
Reset Direct inactive
Hold Time after clock K
Logic Variables
Data In
Enable Clock
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)
1
RESET width (Low)
delay from RESET pad to outputs X or Y
A, B, C, D, E,
1
T
ILO
3.3
2.7
2.2
1.75
1.5
ns
8
T
CKO
T
QLO
2.5
5.2
2.1
4.3
1.7
3.5
1.4
3.1
1.25
2.7
ns
ns
A, B, C, D, E
DI
EC
RD
2
4
6
T
ICK
T
DICK
T
ECCK
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
1.7
1.2
2.3
1.0
1.5
1.0
2.05
1.0
ns
ns
ns
ns
A, B, C, D, E
DI
EC
3
5
7
T
CKI
T
CKDI
T
CKEC
0
1.0
0.8
0
0.9
0.7
0
0.9
0.7
0
0.8
0.6
0
0.7
0.55
ns
ns
ns
11
12
T
CH
T
CL
F
CLK
2.0
2.0
227
1.6
1.6
270
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
13
9
T
RPW
T
RIO
3.2
3.7
2.7
3.1
2.3
2.7
2.3
2.4
2.05
2.15
ns
ns
(XC3142A)
T
MRW
T
MRQ
14.0
14.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
ns
ns
Prelim
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