參數(shù)資料
型號: XC3030A-6PQ100C
廠商: XILINX INC
元件分類: FPGA
英文描述: Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述: FPGA, 100 CLBS, 1500 GATES, 135 MHz, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 55/76頁
文件大?。?/td> 731K
代理商: XC3030A-6PQ100C
R
November 9, 1998 (Version 3.1)
7-57
XC3000 Series Field Programmable Gate Arrays
7
XC3100A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see
XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T
PID
, T
PTG
, and T
PICK
are 3 ns higher for XTL2 when the pin is configured as a user input.
Speed Grade
Symbol
-4
-3
-2
-1
-09
Description
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q)
with latch transparent(XC3100A)Clock (IK)
to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3120A, XC3130A
3
4
T
PID
T
PTG
T
IKRI
2.5
12.0
2.5
2.2
11.0
2.2
2.0
11.0
1.9
1.7
10.0
1.7
1.55
9.2
1.55
ns
ns
ns
XC3142A
XC3164A
XC3190A
XC3195A
1
T
PICK
10.6
10.7
11.0
11.2
11.6
9.4
9.5
9.7
9.9
10.3
8.9
9.0
9.2
9.4
9.8
8.0
8.1
8.3
8.5
8.9
7.2
7.3
7.5
7.7
8.1
ns
ns
ns
ns
ns
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (O) to Pad
same
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(XC3100A)
3-state to Pad
begin hi-Z
same
3-state to Pad
active and valid (fast) (XC3100A)
same
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
(fast)
(slew-rate limited)
(slew -rate limited)
7
7
10
10
9
9
8
8
T
OKPO
T
OKPO
T
OPF
T
OPS
T
TSHZ
T
TSHZ
T
TSON
T
TSON
5.0
12.0
3.7
11.0
6.2
6.2
10.0
17.0
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
3.7
9.7
3.0
8.7
5.0
5.0
8.5
14.2
3.4
8.4
3.0
8.0
4.5
4.5
6.5
11.5
3.3
6.9
2.9
6.5
4.05
4.05
5.0
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
(XC3100A)
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays
RESET Pad to Registered In
5
6
T
OOK
T
OKO
4.5
0
3.6
0
3.2
0
2.9
ns
ns
11
12
T
IOH
T
IOL
F
CLK
2.0
2.0
227
1.6
1.6
270
1.3
1.3
323
1.3
1.3
323
1.3
1.3
370
ns
ns
MHz
(Q)
(XC3142A)
(XC3190A)
(fast)
RESET Pad to output pad
(slew-rate limited)
13
15
15
T
RRI
T
RPO
T
RPO
15.0
25.5
20.0
27.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
23.0
13.0
21.0
17.0
22.0
14.4
21.0
17.0
21.0
ns
ns
ns
ns
Preliminary
相關(guān)PDF資料
PDF描述
XC3142L-2PC84C XTAL MTL T/H HC49/US
XC3142L-3PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3142L-3TQ144C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3142L-3VQ160C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190L-2PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3030A-6VQ100C 制造商:Xilinx 功能描述:
XC3030A-6VQ64C 制造商:Xilinx 功能描述:
XC3030A-7PC44C 功能描述:IC LOGIC CL ARRAY 3000GAT 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
XC3030A-7PC44I 制造商:Xilinx 功能描述:
XC3030A-7PC68C 制造商:Xilinx 功能描述: