V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� XC2S50-5TQ144C
寤犲晢锛� Xilinx Inc
鏂囦欢闋佹暩(sh霉)锛� 97/99闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 2.5V 384 CLB'S 144-TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� Spartan®-II
LAB/CLB鏁�(sh霉)锛� 384
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1728
RAM 浣嶇附瑷堬細 32768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 92
闁€鏁�(sh霉)锛� 50000
闆绘簮闆诲锛� 2.375 V ~ 2.625 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 144-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
鍏跺畠鍚嶇ū锛� 122-1225
XC2S50-5TQ144C-ND
Spartan-II FPGA Family: Pinout Tables
DS001-4 (v2.8) June 13, 2008
Module 4 of 4
Product Specification
97
R
VCCO
1
P156
VCCO
Bank 1*
VCCO
Bank 1*
-
TDO
2
P157
B14
A21
-
GND
-
P158
GND*
-
TDI
-
P159
A15
B20
-
I/O (CS)
1
P160
B13
C19
0
I/O (WRITE)
1
P161
C13
A20
3
I/O
1
-
B19
9
I/O
1
-
C18
12
I/O
1
-
C12
D17
15
GND
-
GND*
-
I/O, VREF
1
P162
A14
A19
18
I/O
1
-
B18
21
I/O
1
-
E16
27
I/O
1
-
D12
C17
30
I/O
1
P163
B12
D16
33
GND
-
GND*
-
VCCO
1-
VCCO
Bank 1*
VCCO
Bank 1*
-
I/O, VREF
1
P164
C11
A18
36
I/O
1
P165
A13
B17
39
I/O
1
-
E15
42
I/O
1
-
A17
45
I/O
1
-
D11
D15
48
GND
-
GND*
-
I/O
1
P166
A12
C16
51
I/O
1
-
D14
54
I/O, VREF
1
P167
E11
E14
60
I/O
1
P168
B11
A16
63
GND
-
P169
GND*
-
VCCO
1
P170
VCCO
Bank 1*
VCCO
Bank 1*
-
VCCINT
-
P171
VCCINT*VCCINT*-
I/O
1
P172
A11
C15
66
I/O
1
P173
C10
B15
69
I/O
1
-
E13
72
I/O
1
-
A15
75
I/O
1
-
F12
78
GND
-
GND*
-
I/O
1
P174
B10
C14
81
I/O
1
-
B14
84
I/O
1
-
A14
87
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
PQ208
FG256
FG456
Bndry
Scan
Function
Bank
I/O
1
P175
D10
D13
90
I/O
1
P176
A10
C13
93
GND
-
P177
GND*
-
VCCO
1-
VCCO
Bank 1*
VCCO
Bank 1*
-
I/O, VREF
1
P178
B9
B13
96
I/O
1
P179
E10
E12
99
I/O
1
-
A13
105
I/O
1
-
A9
B12
108
I/O
1
P180
D9
D12
111
I/O
1
-
C12
114
I/O
1
P181
A8
D11
120
I, GCK2
1
P182
C9
A11
126
GND
-
P183
GND*
-
VCCO
1
P184
VCCO
Bank 1*
VCCO
Bank 1*
-
VCCO
0
P184
VCCO
Bank 0*
VCCO
Bank 0*
-
I, GCK3
0
P185
B8
C11
127
VCCINT
-
P186
VCCINT*VCCINT*-
I/O
0
-
E11
137
I/O
0
P187
A7
A10
140
I/O
0
-
D8
B10
143
I/O
0
-
F11
146
I/O
0
P188
A6
C10
152
I/O, VREF
0
P189
B7
A9
155
VCCO
0-
VCCO
Bank 0*
VCCO
Bank 0*
-
GND
-
P190
GND*
-
I/O
0
P191
C8
B9
158
I/O
0
P192
D7
E10
161
I/O
0
-
C9
164
I/O
0
-
D10
167
I/O
0
P193
E7
A8
170
GND
-
GND*
-
I/O
0
-
D9
173
I/O
0
-
B8
176
I/O
0
-
C8
179
I/O
0
P194
C7
E9
182
I/O
0
P195
B6
A7
185
VCCINT
-
P196
VCCINT*VCCINT*-
VCCO
0
P197
VCCO
Bank 0*
VCCO
Bank 0*
-
XC2S200 Device Pinouts (Continued)
XC2S200 Pad Name
PQ208
FG256
FG456
Bndry
Scan
Function
Bank
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XC2S50-5TQ144C-ES 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:2S50-5TQ144C-ES
XC2S50-5TQ144I 鍔熻兘鎻忚堪:IC FPGA 2.5V I-TEMP 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Spartan®-II 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:Spartan® 6 LX LAB/CLB鏁�(sh霉):3411 閭忚集鍏冧欢/鍠厓鏁�(sh霉):43661 RAM 浣嶇附瑷�:2138112 杓稿叆/杓稿嚭鏁�(sh霉):358 闁€鏁�(sh霉):- 闆绘簮闆诲:1.14 V ~ 1.26 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:676-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:676-FBGA锛�27x27锛�
XC2S50-5TQG144C 鍔熻兘鎻忚堪:IC SPARTAN-II FPGA 50K 144-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Spartan®-II 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�:221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241
XC2S50-5TQG144I 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 144TQFP EP - Trays 鍒堕€犲晢:Xilinx 鍔熻兘鎻忚堪:IC SYSTEM GATE
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