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參數(shù)資料
| 型號： | XC2S400E-7FT256C |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XC2S400E-7FT256C |
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
DS077-3 (v2.0) November 18, 2002
Product Specification
www.xilinx.com
1-800-255-7778
7
R
IOB Input Switching Characteristics
(1)
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in
IOB Input Delay Adjustments for Different Standards
, page 8
.
Symbol
Description
Device
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Propagation Delays
T
IOPI
T
IOPID
T
IOPLI
Pad to I output, no delay
Pad to I output, with delay
Pad to output IQ via transparent latch,
no delay
Pad to output IQ via transparent latch,
with delay
All
All
All
0.4
0.5
0.7
0.8
1.0
1.5
0.4
0.5
0.7
0.8
1.0
1.6
ns
ns
ns
T
IOPLID
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1.3
1.3
1.3
1.3
1.3
1.4
1.5
3.0
3.0
3.2
3.2
3.2
3.2
3.5
1.3
1.3
1.3
1.3
1.3
1.4
1.5
3.1
3.1
3.3
3.3
3.3
3.4
3.7
ns
ns
ns
ns
ns
ns
ns
Sequential Delays
T
IOCKIQ
Setup/Hold Times with Respect to Clock CLK
T
IOPICK
/ T
IOICKP
Pad, no delay
T
IOPICKD
/ T
IOICKPD
Pad, with delay
Clock CLK to output IQ
All
0.1
0.7
0.1
0.7
ns
All
1.4 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
0.7 / 0.01
-
-
-
-
-
-
-
-
-
1.5 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
0.7 / 0.01
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
All
T
IOICECK
/ T
IOCKICE
ICE input
Set/Reset Delays
T
IOSRCKI
T
IOSRIQ
T
GSRQ
Notes:
1.
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table
Delay Measurement Methodology
, page 11
.
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
All
All
All
0.9
0.5
3.8
-
1.0
0.5
3.8
-
ns
ns
ns
1.2
8.5
1.4
9.7
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相關(guān)代理商/技術(shù)參數(shù) |
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