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參數(shù)資料
| 型號： | XC2S15-5VQ100I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 49/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2.5V I-TEMP 100-VQFP |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 96 |
| 邏輯元件/單元數(shù)： | 432 |
| RAM 位總計： | 16384 |
| 輸入/輸出數(shù)： | 60 |
| 門數(shù)： | 15000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
53
R
Power-On Requirements
Spartan-II FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can
consume more than ICCPO minimum, though this cannot
adversely affect reliability.
A maximum limit for ICCPO is not specified. Therefore the
use of foldback/crowbar supplies and fuses deserves
special attention. In these cases, limit the ICCPO current to a
level below the trip point for over-current protection in order
to avoid inadvertently shutting down the supply.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol
Description
Conditions
New
Requirements(1)
For Devices with
Date Code 0321
or Later
Old
Requirements(1)
For Devices with
Date Code
before 0321
Units
Junction
Temperature(2)
Device
Temperature
Grade
Min
Max
Min
Max
I CCPO(3)
Total VCCINT supply
current required
during power-on
–40°C
≤ TJ<–20°C
Industrial
1.50
-
2.00
-
A
–20°C
≤ TJ < 0°C
Industrial
1.00
-
2.00
-
A
0°C
≤ TJ ≤ 85°C
Commercial
0.25
-
0.50
-
A
85°C < TJ ≤ 100°C
Industrial
0.50
-
0.50
-
A
TCCPO(4,5) VCCINT ramp time
–40°C
≤ TJ≤ 100°C
All
-
50
-
50
ms
Notes:
1.
The date code is printed on the top of the device’s package. See the "Device Part Marking" section in Module 1.
2.
The expected TJ range for the design determines the ICCPO minimum requirement. Use the applicable ranges in the junction
temperature column to find the associated current values in the appropriate new or old requirements column according to the date
code. Then choose the highest of these current values to serve as the minimum ICCPO requirement that must be met. For example,
if the junction temperature for a given design is -25°C
≤ TJ ≤ 75°C, then the new minimum ICCPO requirement is 1.5A.
If 5°C
≤ TJ ≤ 90°C, then the new minimum ICCPO requirement is 0.5A.
3.
The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 2.5V.
4.
The ramp time is measured from GND to VCCINT max on a fully loaded board.
5.
During power-on, the VCCINT ramp must increase steadily in voltage with no dips.
6.
For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL(1)
–0.5
0.8
2.0
5.5
0.4
2.4
24
–24
LVCMOS2
–0.5
0.7
1.7
5.5
0.4
1.9
12
–12
PCI, 3.3V
–0.5
44% VCCINT
60% VCCINT
VCCO + 0.5
10% VCCO
90% VCCO
Note (2)
PCI, 5.0V
–0.5
0.8
2.0
5.5
0.55
2.4
Note (2)
GTL
–0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
N/A
40
N/A
GTL+
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
N/A
36
N/A
HSTL I
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
8
–8
HSTL III
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
24
–8
HSTL IV
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
48
–8
SSTL3 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
8
–8
SSTL3 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
16
–16
SSTL2 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
7.6
–7.6
SSTL2 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
15.2
–15.2
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| XC2S15-5VQG100C | 功能描述:IC SPARTAN-II FPGA 15K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
| XC2S15-5VQG100I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 15K GATES 432 CELLS 263MHZ 2.5V 100VTQFP - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S15-6CS144C | 功能描述:IC FPGA 2.5V C-TEMP 144-CSBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC2S15-6CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S15-6CSG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
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