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參數(shù)資料
| 型號(hào)： | XC2S100E-6TQG144C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 19/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 600 CLB'S 144-TQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 600 |
| 邏輯元件/單元數(shù)： | 2700 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 102 |
| 門數(shù)： | 100000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 122-1462 |
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18
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. The phase-shifted output have optional
duty-cycle correction (Figure 13).
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple Spar-
tan-IIE devices.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock. If the DLL uses external feed-
back, apply a reset after startup to ensure consistent lock-
ing to the external signal. See Xilinx Application Note
XAPP174 for more information on DLLs.
Boundary Scan
Spartan-IIE devices support all the mandatory bound-
ary-scan instructions specified in the IEEE standard 1149.1.
A Test Access Port (TAP) and registers are provided that
implement the EXTEST, INTEST, SAMPLE/PRELOAD,
BYPASS, IDCODE, and HIGHZ instructions. The TAP also
supports two USERCODE instructions, internal scan
chains, and configuration/readback of the device.
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO for
Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail
between ground and VCCO. The boundary-scan input pins
(TDI, TMS, TCK) do not have a VCCO requirement and oper-
ate with either 2.5V or 3.3V input signaling levels. TDI, TMS,
and TCK hava a default internal weak pull-up resistor, and
TDO has no default resistor. Bitstream options allow setting
any of the four TAP pins to have an internal pull-up,
pull-down, or neither.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including unbonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
Table 8 lists the boundary-scan instructions supported in
Spartan-IIE FPGAs. Internal signals can be captured during
EXTEST by connecting them to unbonded or unused IOBs.
They may also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Figure 12: Delay-Locked Loop Block Diagram
Figure 13: DLL Output Characteristics
Clock
Distribution
Network
Variable
Delay Line
CLKOUT
Control
CLKFB
CLKIN
ds077-2_10_070203
x132_07_092599
CLKIN
CLK2X
CLK0
CLK90
CLK180
CLK270
CLKDV
CLKDV_DIVIDE=2
DUTY_CYCLE_CORRECTION=FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION=TRUE
t
0
90 180 270
0
90 180 270
Table 8: Boundary-Scan Instructions
Boundary-Scan
Command
Binary
Code[4:0]
Description
EXTEST
00000
Enables boundary-scan
EXTEST operation
SAMPLE/
PRELOAD
00001
Enables boundary-scan
SAMPLE/PRELOAD
operation
USER1
00010
Access user-defined
register 1
USER2
00011
Access user-defined
register 2
CFG_OUT
00100
Access the
configuration bus for
Readback
CFG_IN
00101
Access the
configuration bus for
Configuration
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