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參數(shù)資料
| 型號： | XA2S300E-6FT256Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-IIE 256FPBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-IIE XA |
| LAB/CLB數(shù)： | 1536 |
| 邏輯元件/單元數(shù)： | 6912 |
| RAM 位總計： | 65536 |
| 輸入/輸出數(shù)： | 182 |
| 門數(shù)： | 300000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering
2
DS106-1 (v2.0) August 9, 2013
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
General Overview
The Spartan-IIE family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. The XC2S400E has four col-
umns of block RAM. These functional elements are inter-
connected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-IIE FPGAs are customized by loading configura-
tion data into internal static memory cells. Unlimited repro-
gramming cycles are possible with this approach. Stored
values in these cells determine logic functions and intercon-
nections implemented in the FPGA. Configuration data can
be read from an external serial PROM (master serial mode),
or written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes.
Spartan-IIE FPGAs are typically used in high-volume appli-
cations where the versatility of a fast programmable solution
adds benefits. Spartan-IIE FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
Spartan-IIE FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-IIE devices provide system clock
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-IIE
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
Spartan-IIE Family Compared to Spartan-II
Family
Higher density and more I/O
Higher performance
Unique pinouts in cost-effective packages
Differential signaling
-
LVDS, Bus LVDS, LVPECL
VCCINT = 1.8V
-Lower power
-
5V tolerance with external resistor
-
3V tolerance directly
LVTTL and LVCMOS2 input buffers powered by VCCO
instead of VCCINT
Unique larger bitstream
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