FN8214.1 October 25, 2005 D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions) Notes: 1. DAC input Byte = FFh, Source or sink mode." />
參數(shù)資料
型號(hào)： X96010V14IZ
廠商： Intersil
文件頁(yè)數(shù)： 22/26頁(yè)
文件大?。?/td> 0K
描述： IC SENSOR CONDITIONER 14-TSSOP
標(biāo)準(zhǔn)包裝： 95
類型： 傳感器調(diào)節(jié)器
輸入類型： 電壓
輸出類型： 電壓
接口： 2 線
電流 - 電源： 15mA
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1246 (CN2011-ZH PDF)
5
FN8214.1
October 25, 2005
D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)
Notes: 1.
DAC input Byte = FFh, Source or sink mode.
2.
LSB is defined as
divided by the resistance between R1 or R2 to Vss.
3.
OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.
DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNLDAC.
INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
4.
These parameters are periodically sampled and not 100% tested.
5.
V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies <1%.
6.
The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance volt-
age changes to 2.5V from the sourcing rail, and the current variation is <1%.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
IFS
I1 or I2 full scale current
1.56
1.58
1.6
mA
See note 1, 5, R = 510
3.2
mA
See note 1, 4, 6, R = 255
OffsetDAC
I1 or I2 D/A converter offset error
1
LSB
See notes 2 and 3.
FSErrorDAC
I1 or I2 D/A converter full scale error
-2
2
LSB
DNLDAC
I1 or I2 D/A converter
Differential Nonlinearity
-0.5
0.5
LSB
INLDAC
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
-1
1
LSB
VISink
I1 or I2 Sink Voltage Compliance
1.2
Vcc
V
See note 5
2.5
Vcc
V
See note 4, 6
VISource
I1 or I2 Source Voltage Compliance
0
Vcc-1.2
V
See note 5
0
Vcc-2.5
V
See note 4, 6
IOVER
I1 or I2 overshoot on D/A Converter
data byte transition
0
A
DAC input byte changing from
00h to FFh and vice
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
See note 4.
IUNDER
I1 or I2 undershoot on D/A Converter
data byte transition
0
A
trDAC
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
530
s
TCOIout
Temperataure coefficient of output
current due to internal parameters
-100
+100
ppm/
°C
VRMbit = “0”
2
3
V(VRef)
255
x
[]
X96010
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