參數(shù)資料
型號(hào): X93254UV14I-3
廠商: Intersil
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 0K
描述: IC DCP DUAL 50K 32TAP 14-TSSOP
標(biāo)準(zhǔn)包裝: 95
系列: XDCP™
接片: 32
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±35 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 6 線串行(芯片選擇,遞增,增/減)
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
1
FN8186.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X93254
Dual Digitally Controlled Potentiometers
(XDCPs)
The Intersil X93254 is a dual digitally controlled
potentiometer (XDCP). The device consists of two resistor
arrays, wiper switches, a control section, and nonvolatile
memory. The wiper positions are controlled by individual
Up/Down interfaces.
A potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. The position of each wiper element is controlled by
a set of independent CS, U/D, and INC inputs. The position
of the wiper can be stored in nonvolatile memory and then
be recalled upon during a subsequent power-up operation.
Each potentiometer is connected as a two-terminal variable
resistor and can be used in a wide variety of applications
including:
Bias and Gain control
LCD Contrast Adjustment
Pinout
X93254
(14 LD TSSOP)
TOP VIEW
Features
Dual solid-state potentiometers
Independent Up/Down interfaces
32 wiper tap points per potentiometer
- Wiper position stored in nonvolatile memory and
recalled on power-up
31 resistive elements per potentiometer
- Temperature compensated
- Maximum resistance tolerance of ± 30%
- Terminal voltage, 0 to VCC
Low power CMOS
-VCC = 3V ±10%
- Active current, 250A max
- Standby current, 1A max
High reliability
- Endurance 200,000 data changes per bit
- Register data retention, 100 years
RTOTAL value = 50kΩ
14 Ld TSSOP package
VCC
CS1
INC2
U/D2
RH2
VSS
1
2
3
4
8
7
6
5
RL1
DNC*
*Do not connect.
CS2
INC1
U/D1
RH1
RL2
DNC*
14
13
12
11
9
10
Ordering Information
PART NUMBER
PART MARKING VCC LIMITS (V)
RTOTAL (kΩ)
TEMP
RANGE (°C)
PACKAGE
PKG DWG. #
X93254UV141-3
X9325 4UVE
3 ±10%
50
-40 to +85
14 Ld TSSOP
M14.173
Data Sheet
February 4, 2008
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