參數(shù)資料
型號: X9279TV14ZT1
廠商: Intersil
文件頁數(shù): 18/18頁
文件大?。?/td> 0K
描述: IC XDCP SGL 256TAP 100K 14-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: XDCP™
接片: 256
電阻(歐姆): 100k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
9
FN8175.4
September 23, 2009
These commands only valid when P1 = P0 = 0
S
T
A
R
T
0
101
0 A2
A0
A
C
K
I3
I2
I1
I0
RB RA P1
A
C
K
SCL
SDA
S
T
O
P
00
ID3 ID2
ID1 ID0
P0
Device ID
Internal
Instruction
Opcode
Address
Register
Address
Pot/Bank
Address
A1
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
I3
I2
I1
I0
RB RA
0
ID3 ID2 ID1 ID0
Device ID
External
Instruction
Opcode
Address
Register
Address
Pot/Bank
Address
0
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register D[7:0] for all values of P1 and P0
S
T
A
R
T
01
0
1
A2
A1
A0
A
C
K
P1
P0
A
C
K
SCL
SDA
S
T
O
P
A
C
K
D7
D6 D5 D4
D3
D2
D1 D0
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
I3
I2
I1
I0
0
ID3
ID2
ID1
ID0
Device ID
External
Instruction
Opcode
Address
Register
Address
Pot/Bank
Address
0
S
T
A
R
T
01
A2
A1
A0
A
C
K
RA
P1
P0
A
C
K
SCL
SDA
S
T
O
P
II
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
RB
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
N
C
1
SCL
SD A
VW/RW
INC/DEC
CMD
ISSUED
VOLTAGE OUT
tWRID
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
X9279
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