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參數(shù)資料
| 型號： | X88C75PM |
| 英文描述： | Port Expander and E2 Memory |
| 中文描述： | 端口擴展和E2內存 |
| 文件頁數(shù)： | 7/27頁 |
| 文件大?。?/td> | 125K |
| 代理商： | X88C75PM |
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X88C75 SLIC
E
2
7
Figure 7. On-Chip Registers
Programmable Address Decoding
The X88C75 features an internal programmable ad-
dress decoder which allows the nonvolatile memory
array and the internal registers to be mapped in various
locations of the 64K-byte memory map. The register set
is mappable into a 1K-byte block, while the nonvolatile
memory array is mappable into an 8K-byte block. The
mapping is controlled by two nonvolatile configuration
registers, the SFR Map Register and the E
2
Memory
Map Register. Their bits are mapped as follows:
SFR Map Register (SFRM)
Default = 3F
0
0
A15
A14
A13
A12
A11
A10
7
6
2887 ILL F10
5
4
3
2
1
0
A15-A10
The A15-A10 are upper address bits for the 1K-byte
page where the SFR memory is mapped.
0
2887 ILL F30.2
0
LAM
0
RST
A15
A14
A13
7
6
5
4
3
2
1
0
FC38
EEM*
E
2
Memory Map Register
MSB
LSB
FC08
PDRB
Port Data Register B
MSB
LSB
FC10
PDRA
Port Data Register A
INT
INTA INTB
ENA
ENB ENEE
0
EOW
FC18
ISR
Interrupt Status Register
IRST
1
AWO BWO DIRA DIRB STRA STRB
FC20
CR
Configuration Register
MSB
LSB
FC28
PPRB
Port Pin Register B
MSB
LSB
FC30
PPRA
Port Pin Register A
Special Function Register
Memory Map Register
0
NOTE: * The value returned by reading these registers is the complement of the
actual data. These registers are nonvolatile and a special SDP sequence
is used to alter their contents. All the other registers are initialized by a
valid reset input signal and when the device is power cycled.
0
A15
A14
A13
A12
A11
A10
FC00
SFRM*
FE00
FE0F
16 Bytes General Purpose SRAM
MSB
LSB
MSB
LSB
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