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參數(shù)資料
| 型號(hào)： | X86C64PM |
| 英文描述： | E2 Micro-Peripheral |
| 中文描述： | E2微型外設(shè) |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | X86C64PM |
X86C64
Microcontroller Family Compatible
1
CONTROL
LOGIC
SOFTWARE
DATA
PROTECT
CE
R/W
DS
SEL
A8–A11
AS
L
A
T
C
H
E
S
D
E
C
O
D
E
A12
A12
M
U
X
1K BYTES
1K BYTES
1K BYTES
1K BYTES
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
WC
1K BYTES
1K BYTES
1K BYTES
1K BYTES
A12
X
Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
Characteristics subject to change without notice
E
2
Micro-Peripheral
FEATURES
CONCURRENT READ WRITE
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8
Family
High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
60 mA Maximum Active
200
μ
A Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
64K
X86C64
8192 x 8 Bit
DESCRIPTION
The X86C64 is an 8K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
Preliminary Information
Z8
is a registered trademark of Zilog Corporation
CONCURRENT READ WRITE
is a trademark of Xicor, Inc.
FUNCTIONAL DIAGRAM
3819 FHD F02
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X86C64S | E2 Micro-Peripheral |
| X86C64SI | E2 Micro-Peripheral |
| X86C64SM | E2 Micro-Peripheral |
| X88257 | E2 Micro-Peripheral |
| X88257J | E2 Micro-Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X86C64S | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X86C64SI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X86C64SM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X8701-10 | 制造商:Cooper Crouse-Hinds 功能描述: |
| X8701-3 | 制造商:Cooper Crouse-Hinds 功能描述: |
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