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參數(shù)資料
| 型號： | X4005S8 |
| 英文描述： | SCR Thyristor; Package/Case:B10; Current, It av:760A; Current, It rms:1600A; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Peak Surge Current:15000A; Repetitive Reverse Voltage Max, Vrrm:1600V |
| 中文描述： | CPU監(jiān)控 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 378K |
| 代理商： | X4005S8 |
X4003/X4005
Characteristics subject to change without notice.
9 of 18
REV 1.1.3 4/30/02
www.xicor.com
Serial Read Operations
The read operation allows the master to access the control
register. To conform to the I
2
C standard, prior to issuing
the slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the byte address. After acknowledging receipt of the
byte address, the master immediately issues another
start condition and the slave address byte with the R/W
bit set to one. This is followed by an acknowledge from
the device and then by the eight bit control register.
The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequences.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
RESET/RESET signal is active for t
PURST
.
Figure 9. Control Register Read Sequence
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow a write operation.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the control register to change watchdog timer or
block lock settings.
– The WP pin, when held HIGH, prevents all writes to
the control register.
– Communication to the device is inhibited below the
V
TRIP
voltage.
– Command to change the control register are termi-
nated if in-progress when RESET/RESET go active.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X4005S8-1.8 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor |
| X4005S8-2.7 | 功能描述:IC SUPERVISOR CPU I2C 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
| X4005S8-2.7A | 功能描述:IC SUPERVISOR CPU I2C 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
| X4005S8-4.5A | 功能描述:IC SUPERVISOR CPU I2C 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
| X4005S8I | 功能描述:IC SUPERVISOR CPU I2C 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
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