參數(shù)資料
型號: X40011S8I-C
英文描述: Dual Voltage Monitor with Integrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 12/25頁
文件大?。?/td> 124K
代理商: X40011S8I-C
X40010/X40011/X40014/X40015 – Preliminary
Characteristics subject to change without notice.
12 of 25
REV 1.3.4 7/12/02
www.xicor.com
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 11. X40010/11/14/15 Addressing
Control Register
Fault Detection Register
1
1
0
0
1
1
1
1
Word Address
Slave Byte
1
0
0
0
0
0
R/W
R/W
Control Register
Fault Detection Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 12. Current Address Read Sequence
.
Figure 13. Random Address Read Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Data
SDA Bus
Signals from
the Slave
Signals from
the Master
1
1 0 1 0
0
0
0
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
1 0 1
0
0
相關(guān)PDF資料
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X40011 Dual Voltage Monitor with Intergrated CPU Supervisor
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