參數(shù)資料
型號: X40011S8-A
英文描述: Dual Voltage Monitor with Integrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 13/25頁
文件大?。?/td> 124K
代理商: X40011S8-A
X40010/X40011/X40014/X40015 – Preliminary
Characteristics subject to change without notice.
13 of 25
REV 1.3.4 7/12/02
www.xicor.com
– One bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for
t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
Figure 14. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
相關PDF資料
PDF描述
X40011S8-B Dual Voltage Monitor with Integrated CPU Supervisor
X40011S8-C Dual Voltage Monitor with Integrated CPU Supervisor
X40011S8I-A Dual Voltage Monitor with Integrated CPU Supervisor
X40011S8I-B Dual Voltage Monitor with Integrated CPU Supervisor
X40011S8I-C Dual Voltage Monitor with Integrated CPU Supervisor
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