參數(shù)資料
型號: X28C513EM-25
廠商: INTERSIL CORP
元件分類: DRAM
英文描述: 5V, Byte Alterable EEPROM
中文描述: 64K X 8 EEPROM 5V, 250 ns, CQCC32
封裝: CERAMIC, LCC-32
文件頁數(shù): 5/25頁
文件大?。?/td> 126K
代理商: X28C513EM-25
X28C512/X28C513
5
The Toggle Bit I/O
6
Figure 3a. Toggle Bit Bus Sequence
Figure 3b. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement
DATA
Polling.
This can be especially helpful in an array comprised of
multiple X28C512/513 memories that is frequently up-
dated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The
timing diagram in Figure 3a illustrates the sequence of
events on the bus. The software flow diagram in Figure
3b illustrates a method for polling the Toggle Bit.
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
X28C512
READY
COMPARE
OK
NO
YES
3856 FHD F10
LAST WRITE
CE
OE
WE
I/O6
X28C512/513
READY
VOH
VOL
LAST
WRITE
HIGH Z
* Beginning and ending state of I/O6 will vary.
*
*
3856 FHD F09.1
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