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參數(shù)資料
| 型號： | X28C513EM-15 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V, Byte Alterable EEPROM |
| 中文描述： | 64K X 8 EEPROM 5V, 150 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 126K |
| 代理商： | X28C513EM-15 |
6
X28C512/X28C513
HARDWARE DATA PROTECTION
The X28C512/513 provides three hardware features
that protect nonvolatile data from inadvertent writes.
Noise Protection—A
WE
pulse typically less than
10ns will not initiate a write cycle.
Default V
CC
Sense—All write functions are inhibited
when V
CC
is
≤
3.6V.
Write Inhibit—Holding either
OE
LOW,
WE
HIGH,
or
CE
HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
SOFTWARE DATA PROTECTION
The X28C512/513 offers a software controlled data
protection feature. The X28C512/513 is shipped from
Xicor with the software data protection NOT ENABLED;
that is, the device will be in the standard operating mode.
In this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
of the device once V
CC
was stable.
The X28C512/513 can be automatically protected dur-
ing power-up and power-down without the need for
external circuits by employing the software data protec-
tion feature. The internal software data protection circuit
is enabled after the first write operation utilizing the
software algorithm. This circuit is nonvolatile and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28C512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data
to the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 4a and 4b for the sequence.
The three byte sequence opens the page write window
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle has
been completed, the device will automatically be re-
turned to the data protected state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X28C513EM-20 | 5V, Byte Alterable EEPROM |
| X28C513EM-25 | 5V, Byte Alterable EEPROM |
| X28C513JI-12T1 | 5V, Byte Alterable EEPROM |
| X28C513JI-15 | 5V, Byte Alterable EEPROM |
| X28C64DI-15 | 5 Volt, Byte Alterable E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28C513EM-20 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513EM-25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513EM-90 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
| X28C513EMB-12 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
| X28C513EMB-15 | 制造商:Intersil Corporation 功能描述: |
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