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參數(shù)資料
| 型號： | X28C513EM-12 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V, Byte Alterable EEPROM |
| 中文描述： | 64K X 8 EEPROM 5V, 120 ns, CQCC32 |
| 封裝： | CERAMIC, LCC-32 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 126K |
| 代理商： | X28C513EM-12 |
14
X28C512/X28C513
CE
Controlled Write Cycle
Notes:
(5) Between successive byte writes within a page write operation,
OE
can be strobed LOW: e.g. this can be done with
CE
and
WE
HIGH
to fetch data from another memory device within the system for the next write; or with
WE
HIGH and
CE
LOW effectively performing
a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform
to either the
CE
or
WE
controlled write cycle timing.
Page Write Cycle
3856 FHD F18
ADDRESS
tAS
tOEH
tWC
tAH
tOES
tWPH
tCS
tDV
tDS
tDH
tCH
CE
WE
OE
DATA IN
DATA OUT
HIGH Z
tCW
DATA VALID
3856 FHD F19.1
WE
OE
(5)
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
tWP
tWPH
tBLC
tWC
CE
*ADDRESS
(6)
I/O
*For each successive write within the page write operation, A7–A15 should be the same or
writes to an unknown address could occur.
LAST BYTE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X28C513EM-15 | 5V, Byte Alterable EEPROM |
| X28C513EM-20 | 5V, Byte Alterable EEPROM |
| X28C513EM-25 | 5V, Byte Alterable EEPROM |
| X28C513JI-12T1 | 5V, Byte Alterable EEPROM |
| X28C513JI-15 | 5V, Byte Alterable EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28C513EM-15 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513EM-20 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513EM-25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513EM-90 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
| X28C513EMB-12 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
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