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X24026
11
WRITE CYCLE LIMITS
7020 FRM T08
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the X24026 bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slave address.
Write Cycle Timing
Notes:
(5) Typical values are for T
A
= 25
°
C and nominal supply voltage (5V)
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
Symbol
t
WR(6)
Parameter
Min.
Typ.
(5)
Max.
Units
Write Cycle Time
5
10
ms
7020 FRM 15
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
CONDITION
START
CONDITION
X24026
ADDRESS
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
7020 FRM 16
120
100
80
40
60
20
20
40
60
80 100 120
0
0
R
)
BUS CAPACITANCE (pF)
MIN.
RESISTANCE
MAX.
RESISTANCE
R
MAX
=C
BUS
t
R
R
MIN
=I
OL MIN
V
CC MAX
=1.8K
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
May change
from High to
Low
Will change
from Low to
High
Will change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance