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參數(shù)資料
| 型號(hào)： | X1228V14Z-4.5A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/29頁 |
| 文件大小： | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 95 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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16
FN8100.4
May 18, 2006
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the
part drops below a fixed vTRIP voltage, a reset pulse is
issued to the host microcontroller. The circuitry moni-
tors the VCC line with a voltage comparator which
senses a preset threshold voltage. Power-up and
power-down waveforms are shown in Figure 4. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
When the low voltage reset signal is active, the operation
of any in progress nonvolatile write cycle is unaffected,
allowing a nonvolatile write to continue as long as possi-
ble (down to the power-on reset voltage). The low volt-
age reset signal, when active, terminates in progress
communications to the device and prevents new com-
mands, to reduce the likelihood of data corruption.
Figure 3. Watchdog Restart/Time Out
Figure 4. Power-on Reset and Low Voltage Reset
VCC THRESHOLD RESET PROCEDURE
[OPTIONAL]
The X1228 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X1228 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile write control signal.
Setting the VTRIP Voltage
It is necessary to reset the trip point before setting the
new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the RESET pin
to the programming voltage VP. Then write data 00h to
address 01h. The stop bit following a valid write opera-
tion initiates the VTRIP programming sequence. Bring
RESET to VCC to complete the operation. Note: this
operation may take up to 10 milliseconds to complete
and also writes 00h to address 01h of the EEPROM
array.
tRSP<tWDO
tRST
RESET
SDA
tRSP
Note: All inputs are ignored during the active reset period (tRST).
tRST
SCL
tRSP>tWDO
Start
Stop Start
VCC
VTRIP
RESET
tPURST
tR
tF
tRPD
VRVALID
X1228
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