參數(shù)資料
型號(hào)： X1209
英文描述： Real Time Clock/Calendar with Event/Timestamp Detection & Alarms(帶有事件/時(shí)間標(biāo)記檢測(cè)與報(bào)警功能的實(shí)時(shí)時(shí)鐘/日歷)
中文描述： 實(shí)時(shí)時(shí)鐘/日歷的事件/時(shí)間戳檢測(cè)
文件頁(yè)數(shù)： 20/27頁(yè)
文件大?。?/td> 511K
代理商： X1209
Preliminary Information
X1209
20 of 27
REV 3.0 2/11/04
www.xicor.com
Figure 5. Acknowledge Response From Receiver
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1209 compares the device identifier
and device select bits with ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the
SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0H,
so a current address read of the CCR array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 6.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. For a random read of the Clock/Control
Registers, the slave byte must be 1101111x in both
places.
Figure 6. Slave Address, Word Address, and Data Bytes
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
0
0
0
0
0
0
0
1
1
0
1
1
1
R/W
1
0
Word Address 1
Byte 1
Word Address 0
Byte 2
相關(guān)PDF資料
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