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    參數(shù)資料
    型號: X1205V8T1
    廠商: Intersil
    文件頁數(shù): 20/22頁
    文件大?。?/td> 0K
    描述: IC RTC/CALENDAR 2-WIRE 8-TSSOP
    標準包裝: 2,500
    類型: 時鐘/日歷
    特點: 警報器,閏年
    時間格式: HH:MM:SS(12/24 小時)
    數(shù)據格式: YY-MM-DD-dd
    接口: I²C,2 線串口
    電源電壓: 2.7 V ~ 5.5 V
    電壓 - 電源,電池: 1.8 V ~ 5.5 V
    工作溫度: 0°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
    供應商設備封裝: 8-TSSOP
    包裝: 帶卷 (TR)
    7
    FN8097.3
    May 2, 2006
    DESCRIPTION (continued)
    The powerful Dual Alarms can be set to any
    Clock/Calendar value for a match. For instance, every
    minute, every Tuesday, or 5:23 AM on March 21. The
    alarms can be polled in the Status Register or provide
    a hardware interrupt (IRQ Pin). There is a repeat
    mode for the alarms allowing a periodic interrupt.
    The device offers a backup power input pin. This
    VBACK pin allows the device to be backed up by
    battery or SuperCap. The entire X1205 device is fully
    operational
    from
    2.7
    to
    5.5
    volts
    and
    the
    clock/calendar portion of the X1205 device remains
    fully operational down to 1.8 volts (Standby Mode).
    PIN DESCRIPTIONS
    Serial Clock (SCL)
    The SCL input is used to clock all data into and out of
    the device. The input buffer on this pin is always active
    (not gated).
    Serial Data (SDA)
    SDA is a bidirectional pin used to transfer data into and
    out of the device. It has an open drain output and may
    be wire ORed with other open drain or open collector
    outputs. The input buffer is always active (not gated).
    An open drain output requires the use of a pull-up
    resistor. The output circuitry controls the fall time of
    the output signal with the use of a slope controlled
    pull-down. The circuit is designed for 400kHz 2-wire
    interface speeds.
    VBACK
    This input provides a backup supply voltage to the
    device. VBACK supplies power to the device in the
    event the VCC supply fails. This pin can be connected
    to a battery, a Supercap or tied to ground if not used.
    Interrupt Output – IRQ
    This is an interrupt signal output. This signal notifies a
    host processor that an alarm has occurred and
    requests action. It is an open drain active low output.
    X1, X2
    The X1 and X2 pins are the input and output,
    respectively, of an inverting amplifier. An external
    32.768kHz quartz crystal is used with the X1205 to
    supply a timebase for the real time clock. The
    recommended crystal is a Citizen CFS206-32.768KDZF.
    Internal compensation circuitry is included to form a
    complete oscillator circuit. Care should be taken in the
    placement of the crystal and the layout of the circuit.
    Plenty of ground plane around the device and short
    traces to X1 and X2 are highly recommended. See
    Application section for more recommendations.
    Figure 2. Recommended Crystal connection
    POWER CONTROL OPERATION
    The power control circuit accepts a VCC and a VBACK
    input. The power control circuit powers the clock from
    VBACK when VCC < VBACK - 0.2V. It will switch back to
    power the device from VCC when VCC exceeds VBACK.
    Figure 3. Power Control
    REAL TIME CLOCK OPERATION
    The Real Time Clock (RTC) uses an external
    32.768kHz quartz crystal to maintain an accurate
    internal representation of second, minute, hour, day,
    date, month, and year. The RTC has leap-year correc-
    tion. The clock also corrects for months having fewer
    than 31 days and has a bit that controls 24 hour or
    AM/PM format. When the X1205 powers up after the
    loss of both VCC and VBACK, the clock will not operate
    until at least one byte is written to the clock register.
    Reading the Real Time Clock
    The RTC is read by initiating a Read command and
    specifying the address corresponding to the register of
    the Real Time Clock. The RTC Registers can then be
    read in a Sequential Read Mode. Since the clock runs
    continuously and a read takes a finite amount of time,
    there is the possibility that the clock could change during
    the course of a read operation. In this device, the time is
    latched by the read command (falling edge of the clock
    NC = No internal connection
    X1
    X2
    VBACK
    VCC
    IRQ
    SCL
    SDA
    VSS
    1
    2
    3
    4
    7
    8
    6
    5
    8-Pin TSSOP
    X1205
    X1
    X2
    VBACK
    VCC
    IRQ
    SCL
    SDA
    VSS
    1
    2
    3
    4
    7
    8
    6
    5
    8-Pin SOIC
    X1
    X2
    VBACK
    In
    Voltage
    VCC
    On
    Off
    X1205
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