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參數(shù)資料
| 型號(hào)： | X1203 |
| 英文描述： | 2-Wire RTC(Real Time Clock)/Calendar/Alarm(實(shí)時(shí)時(shí)鐘/日歷/警報(bào)) |
| 中文描述： | 2線實(shí)時(shí)時(shí)鐘（實(shí)時(shí)時(shí)鐘）/日歷/鬧鐘（實(shí)時(shí)時(shí)鐘/日歷/警報(bào)） |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 84K |
| 代理商： | X1203 |
X1203
11
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the CCR Address Bytes. After acknowledging receipt
of the CCR Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 11. The X1203 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Figure 10. Random Address Read Sequence
0
Slave
Address
CCR
Address 1
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
A
C
K
CCR
Address 0
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 1
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
automatically, allowing the entire register contents to
be serially read during one operation. At the end of the
register space the counter “rolls over” to the first loca-
tion in the register and the device continues to output
data for each acknowledge received. Refer to Figure
12 for the acknowledge and data transfer sequence.
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| X1205 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar |
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