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參數(shù)資料
| 型號(hào)： | WV3EG6434S262BD4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 273K |
| 代理商： | WV3EG6434S262BD4SG |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WV3EG6434S-BD4
April 2005
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
DDR333@
CL=2.5
DDR266@
CL=2
DDR266@
CL=2.5
Parameter
Symbol Conditions
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN);
DQ,DM and DQS inputs changing once per clock cycle; Address
and control inputs changing once every two cycles.
720
640
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN
);tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing
once per clock cycle.
920
840
mA
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power- down mode; tCK=tCK(MIN);
CKE=(low)
24
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high;
Address and other control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
240
200
mA
Precharge Quiet
Standby Current
IDD2Q
CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK = 100Mhz
for DDR200, 133Mhz for DDR266A & DDR266B; Address and
other control inputs stable with keeping >= VIH(min) or =
< VIL(max); VIN = VREF for DQ, DQS and DM
200
185
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode; tCK(MIN); CKE=(low)
280
240
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing
twice per clock cycle; Address and other control inputs changing
once per clock cycle.
440
360
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One device bank
active;Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); Iout = 0mA.
1280
1120
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
1280
1080
mA
Auto Refresh Current
IDD5
tRC=tRC(MIN)
1360
1280
mA
Self Refresh Current
IDD6
CKE 0.2V
24
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto precharge with
tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change
only during Active Read or Write commands.
2240
2080
mA
Note: IDD speicication is based on Samsung components. Other DRAM manufacturers specication may be different.
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