參數(shù)資料
型號: WLA49VVA
廠商: National Semiconductor Corporation
元件分類: ADC
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12.0 Status & Control Registers (Continued)
12.8 PLL N MODULUS CONFIGURATION REGISTER
This register is used to control the modulation applied to the feedback divider of the PLL.
TABLE 9. PLL_N_MOD (0x05h)
Bits
Field
Description
4:0
PLL_N_MOD
Programs the PLL N divider’s fractional component:
PLL_N_MOD
Fractional Addition
0
0/32
1
1/32
2 to 30
2/32 to 30/32
31
31/32
6:5
DITHER_LEVEL
Allows control over the dither used by the N divider:
DITHER_LEVEL
Value
00
2
Medium
01
2
Small
10
2
Large
11
2
Off
7
RSVD
RESERVED
The complete N divider is a fractional divider as such:
N = PLL_N + PLL_N_MOD/32
If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the
following formula:
F
out =(Fin*N)/(M*P)
Note 14: See Further Notes on PLL Programming for more details.
LM4935
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