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參數(shù)資料
| 型號(hào)： | W942504CH-7 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 41/45頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
Publication Release Date: February 14, 2003
- 5 -
Revision A1
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
28
32,
35
42
A0
A12
Address
Multiplexed pins for row and column address.
Row address: A0
A12.
Column address: A0
A9, A11. (A10 is used for Auto Precharge)
26,27
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or bank to
read/write during column address latch time.
5, 11, 56, 62
DQ0
DQ3
Data Input/
Output
The DQ0 – DQ7 input and output data are synchronized with both
edges of DQS.
51
DQS
Data Strobe
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
24
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
23, 22, 21
RAS , CAS ,
WE
Command
Inputs
Command inputs (along with CS ) define the command being
entered.
47
DM
Write mask When DM is asserted "high" in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
45, 46
CLK, CLK
Differential
clock inputs
All address and control input signals are sampled on the crossing
of the positive edge of CLK and negative edge of CLK .
44
CKE
Clock Enable
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode, or Self Refresh mode is
entered.
49
VREF
Reference
Voltage
VREF is reference voltage for inputs.
1, 18, 33
VDD
Power
(+2.5V)
Power for logic circuit inside DDR SDRAM.
34, 48, 66
VSS
Ground
Ground for logic circuit inside DDR SDRAM.
3, 9, 15, 55, 61
VDDQ
Power
(+2.5V) for
I/O buffer
Separated power from VDD, used for output buffer, to improve
noise.
6, 12, 52, 58, 64
VSSQ
Ground for
I/O buffer
Separated ground from VSS, used for output buffer, to improve
noise.
2, 4, 7, 8, 10, 13,
14, 16, 17, 19,
20, 25, 43, 50,
53, 54, 57, 59,
60, 63, 65
NC1, NC2
No
Connection
No connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W942508BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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