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參數(shù)資料
| 型號： | VT83C572 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI TO USB CONTROLLER |
| 中文描述： | PCI到USB控制器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 53K |
| 代理商： | VT83C572 |
VIA Technologies, Inc.
VT83C572
-2-
bit 4:
bit 3:
Memory write and invalidate, default: disabled
Fixed at 0 (special cycles)
Bus master, default: disabled
Memory space, default: disabled
I/O space, default: disabled
bit 2:
bit 1:
bit 0:
7-6
Status Register
reserved
Signaled system error
Received master abort
Received target abort
Signaled target abort
bit 10-9: DEVSEL# timing: fixed at 01 (medium)
bit 8-0: reserved
bit 15:
bit 14:
bit 13:
bit 12:
bit 11:
08
Revision ID.
B-9
Class Code Register:
Fixed at 0C0300h to indicate the USB Controller
0C
Cache Line Size
Default: 00h
0D
Latency Timer
Default: 16h
0E
Header Type = 00h
(read only)
0F
BIST
Fixed at 00
23-20
Base address for
UHCI v1.1
compliant USB IO Registers
bit 31-16:reserved
bit 15-5:Port address for the base USB IO Registers, corresponding to AD[15:5]
bit 4-0: 00001b
3C
Interrupt Line
3D
Interrupt Pin, Default = 01h
3E-3F
reserved
40
Misc. Control Register 1
bit 7:
PCI Memory Command Option
0 - Support Memory Read Line, Memory Read Multiple, Memory Write and Invalidate
1 - Only support Memory Read, Memory Write Commands
bit 6:
Babble Option
0 - Automatically disable babbled port when EOF babble occurs.
1 - Don’t disable babbled port.
bit 5:
PCI Parity Check Option
0 - Disable PERR generation
1 - Enable parity check and PERR generation
bit 4:
reserved
bit 3:
USB Data Length Option
0 - Support TD length up to 1280.
1 - Support TD length up to 1023.
bit 2:
USB Power Management
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