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參數(shù)資料
| 型號： | VSC880 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 路由/交換 |
| 英文描述： | High Performance 16x16 Serial Crosspoint Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA304 |
| 封裝： | BGA-304 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 390K |
| 代理商： | VSC880 |
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VITESSE
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
G52191-0, Rev 4.2
01/05/01
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 4: Switch Configuration Interface Functional Timing (CEN=0)
The switch configuration data for each port is as follows:
F0[3:0] = FI[port9], FI[port8], FI[port1], FI[port0]
F1[3:0] = FI[port11], FI[port10], FI[port3], FI[port2]
F2[3:0] = FI[port13], FI[port12], FI[port5], FI[port4]
F3[3:0] = FI[port15], FI[port14], FI[port7], FI[port6]
C0[15:0] = Port9[3:0], Port8[3:0], Port1[3:0], Port0[3:0]
C1[15:0] = Port11[3:0], Port10[3:0], Port3[3:0], Port2[3:0]
C2[15:0] = Port13[3:0], Port12[3:0], Port5[3:0], Port4[3:0]
C3[15:0] = Port15[3:0], Port14[3:0], Port7[3:0], Port6[3:0]
Where FI[portN] is the Force IDLE bit for port N and PortN[3:0] is the input port number to be connected to output
port N.
1.7 Built-in Self-Test
The switch has built-in self-test logic that can be used to verify the high-speed circuitry as well as the switch
matrix while operating at full speed. The built-in self-test mode is enabled by setting the built-in self-test enable
(BSTEN) signal HIGH. If the signal BSTLPBK is set HIGH and TESTEN is set LOW, it loops all 16 serial outputs
back to the Data Recovery Unit (DRU) at the serial inputs. An internal Pseudo Random Bit Sequence (PRBS)
generator connected to the switch matrix at port 0. The random data is sent to port 0, passed through the switch
matrix, looped back through the serial interface and returned to the data comparator. If this data matches the correct
pattern, BSTPASS is set HIGH. By configuring port 0 to connect to other ports (ports 1 through 15) through the
switch matrix using the parallel configuration interface, the rest of the serial channels (one port at a time) can be
tested in turn. For example, port 0 can be connected to port 1 by configuring the switch matrix. The PRBS generator
transmits the random data through port 0 to port 1, and the random data is then looped back from port 1 to port 0 and
the data comparator. To test all 16 ports, the user will need to configure the switch matrix 16 times to test all ports.
REFCLK
DATA[15:0]
WEN
C0
C1
C3
C2
Switch updated in this cycle
FI[3:0]
F0
F1
F3
F2
CCLK
Min. of 5 Cycles
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相關代理商/技術參數(shù) |
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| VSC880TY | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:High Performance 16x16 Serial Crosspoint Switch |
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